starpu_slu_lu_model_22.idgraf 8.9 KB

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  1. ##################
  2. # Performance Model Version
  3. 45
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 9
  8. ####################
  9. # COMB_8
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3)
  15. 0
  16. ####################
  17. # DEV_0
  18. # device id
  19. 0
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cpu0_impl0 (Comb8)
  29. # number of entries
  30. 3
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # not multiple-regression-base
  36. 0
  37. # hash size flops mean (us) dev (us) sum sum2 n
  38. d46431bb 1228800 0.000000e+00 3.393927e+03 8.566524e+01 3.533078e+06 1.199865e+10 1041
  39. f0ac7beb 4915200 0.000000e+00 2.682238e+04 4.332821e+02 9.951104e+06 2.669820e+11 371
  40. 24c84a50 11059200 0.000000e+00 8.930213e+04 1.450773e+03 2.679064e+07 2.393092e+12 300
  41. ####################
  42. # COMB_5
  43. # number of types devices
  44. 1
  45. ####################
  46. # DEV_0
  47. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3)
  48. 1
  49. ####################
  50. # DEV_0
  51. # device id
  52. 1
  53. ####################
  54. # DEV_0
  55. # number of cores
  56. 1
  57. ##########
  58. # number of implementations
  59. 1
  60. #####
  61. # Model for cuda1_impl0 (Comb5)
  62. # number of entries
  63. 3
  64. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  65. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  66. # a b c
  67. nan nan nan
  68. # not multiple-regression-base
  69. 0
  70. # hash size flops mean (us) dev (us) sum sum2 n
  71. d46431bb 1228800 0.000000e+00 1.946363e+02 2.537099e+01 6.294539e+05 1.245963e+08 3234
  72. f0ac7beb 4915200 0.000000e+00 9.257288e+02 6.590058e+01 3.791785e+06 3.527953e+09 4096
  73. 24c84a50 11059200 0.000000e+00 2.991139e+03 1.645886e+02 1.221282e+07 3.664085e+10 4083
  74. ####################
  75. # COMB_0
  76. # number of types devices
  77. 1
  78. ####################
  79. # DEV_0
  80. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3)
  81. 1
  82. ####################
  83. # DEV_0
  84. # device id
  85. 4
  86. ####################
  87. # DEV_0
  88. # number of cores
  89. 1
  90. ##########
  91. # number of implementations
  92. 1
  93. #####
  94. # Model for cuda4_impl0 (Comb0)
  95. # number of entries
  96. 3
  97. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  98. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  99. # a b c
  100. nan nan nan
  101. # not multiple-regression-base
  102. 0
  103. # hash size flops mean (us) dev (us) sum sum2 n
  104. d46431bb 1228800 0.000000e+00 1.954243e+02 2.831383e+01 5.661443e+05 1.129608e+08 2897
  105. f0ac7beb 4915200 0.000000e+00 9.376794e+02 7.341921e+01 3.415966e+06 3.222718e+09 3643
  106. 24c84a50 11059200 0.000000e+00 2.995872e+03 1.614697e+02 1.133938e+07 3.407000e+10 3785
  107. ####################
  108. # COMB_1
  109. # number of types devices
  110. 1
  111. ####################
  112. # DEV_0
  113. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3)
  114. 1
  115. ####################
  116. # DEV_0
  117. # device id
  118. 6
  119. ####################
  120. # DEV_0
  121. # number of cores
  122. 1
  123. ##########
  124. # number of implementations
  125. 1
  126. #####
  127. # Model for cuda6_impl0 (Comb1)
  128. # number of entries
  129. 3
  130. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  131. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  132. # a b c
  133. nan nan nan
  134. # not multiple-regression-base
  135. 0
  136. # hash size flops mean (us) dev (us) sum sum2 n
  137. d46431bb 1228800 0.000000e+00 1.867261e+02 2.556099e+01 5.342234e+05 1.016227e+08 2861
  138. f0ac7beb 4915200 0.000000e+00 8.996740e+02 6.639270e+01 3.427758e+06 3.100659e+09 3810
  139. 24c84a50 11059200 0.000000e+00 2.987519e+03 1.530428e+02 1.113747e+07 3.336072e+10 3728
  140. ####################
  141. # COMB_3
  142. # number of types devices
  143. 1
  144. ####################
  145. # DEV_0
  146. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3)
  147. 1
  148. ####################
  149. # DEV_0
  150. # device id
  151. 0
  152. ####################
  153. # DEV_0
  154. # number of cores
  155. 1
  156. ##########
  157. # number of implementations
  158. 1
  159. #####
  160. # Model for cuda0_impl0 (Comb3)
  161. # number of entries
  162. 3
  163. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  164. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  165. # a b c
  166. nan nan nan
  167. # not multiple-regression-base
  168. 0
  169. # hash size flops mean (us) dev (us) sum sum2 n
  170. d46431bb 1228800 0.000000e+00 1.927028e+02 2.478568e+01 6.783137e+05 1.328754e+08 3520
  171. f0ac7beb 4915200 0.000000e+00 9.234475e+02 6.432680e+01 3.846159e+06 3.568960e+09 4165
  172. 24c84a50 11059200 0.000000e+00 2.982449e+03 1.542480e+02 1.210278e+07 3.619247e+10 4058
  173. ####################
  174. # COMB_2
  175. # number of types devices
  176. 1
  177. ####################
  178. # DEV_0
  179. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3)
  180. 1
  181. ####################
  182. # DEV_0
  183. # device id
  184. 5
  185. ####################
  186. # DEV_0
  187. # number of cores
  188. 1
  189. ##########
  190. # number of implementations
  191. 1
  192. #####
  193. # Model for cuda5_impl0 (Comb2)
  194. # number of entries
  195. 3
  196. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  197. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  198. # a b c
  199. nan nan nan
  200. # not multiple-regression-base
  201. 0
  202. # hash size flops mean (us) dev (us) sum sum2 n
  203. d46431bb 1228800 0.000000e+00 1.868734e+02 2.558187e+01 5.049318e+05 9.612659e+07 2702
  204. f0ac7beb 4915200 0.000000e+00 9.407115e+02 6.874274e+01 3.317889e+06 3.137844e+09 3527
  205. 24c84a50 11059200 0.000000e+00 2.972987e+03 1.569773e+02 1.177600e+07 3.510750e+10 3961
  206. ####################
  207. # COMB_6
  208. # number of types devices
  209. 1
  210. ####################
  211. # DEV_0
  212. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3)
  213. 1
  214. ####################
  215. # DEV_0
  216. # device id
  217. 3
  218. ####################
  219. # DEV_0
  220. # number of cores
  221. 1
  222. ##########
  223. # number of implementations
  224. 1
  225. #####
  226. # Model for cuda3_impl0 (Comb6)
  227. # number of entries
  228. 3
  229. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  230. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  231. # a b c
  232. nan nan nan
  233. # not multiple-regression-base
  234. 0
  235. # hash size flops mean (us) dev (us) sum sum2 n
  236. d46431bb 1228800 0.000000e+00 1.924732e+02 2.459364e+01 6.245755e+05 1.221768e+08 3245
  237. f0ac7beb 4915200 0.000000e+00 9.173887e+02 7.039530e+01 3.781476e+06 3.489510e+09 4122
  238. 24c84a50 11059200 0.000000e+00 3.001859e+03 1.612679e+02 1.156916e+07 3.482922e+10 3854
  239. ####################
  240. # COMB_4
  241. # number of types devices
  242. 1
  243. ####################
  244. # DEV_0
  245. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3)
  246. 1
  247. ####################
  248. # DEV_0
  249. # device id
  250. 7
  251. ####################
  252. # DEV_0
  253. # number of cores
  254. 1
  255. ##########
  256. # number of implementations
  257. 1
  258. #####
  259. # Model for cuda7_impl0 (Comb4)
  260. # number of entries
  261. 3
  262. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  263. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  264. # a b c
  265. nan nan nan
  266. # not multiple-regression-base
  267. 0
  268. # hash size flops mean (us) dev (us) sum sum2 n
  269. d46431bb 1228800 0.000000e+00 1.877972e+02 2.764994e+01 5.324050e+05 1.021516e+08 2835
  270. f0ac7beb 4915200 0.000000e+00 9.245688e+02 6.946750e+01 3.363581e+06 3.127419e+09 3638
  271. 24c84a50 11059200 0.000000e+00 3.005524e+03 1.690713e+02 1.154422e+07 3.480621e+10 3841
  272. ####################
  273. # COMB_7
  274. # number of types devices
  275. 1
  276. ####################
  277. # DEV_0
  278. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3)
  279. 1
  280. ####################
  281. # DEV_0
  282. # device id
  283. 2
  284. ####################
  285. # DEV_0
  286. # number of cores
  287. 1
  288. ##########
  289. # number of implementations
  290. 1
  291. #####
  292. # Model for cuda2_impl0 (Comb7)
  293. # number of entries
  294. 3
  295. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  296. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  297. # a b c
  298. nan nan nan
  299. # not multiple-regression-base
  300. 0
  301. # hash size flops mean (us) dev (us) sum sum2 n
  302. d46431bb 1228800 0.000000e+00 1.865351e+02 2.381101e+01 6.651841e+05 1.261020e+08 3566
  303. f0ac7beb 4915200 0.000000e+00 9.257403e+02 6.896157e+01 3.669635e+06 3.415980e+09 3964
  304. 24c84a50 11059200 0.000000e+00 3.007743e+03 1.477912e+02 1.238889e+07 3.735258e+10 4119