starpu_dlu_lu_model_22.idgraf 8.9 KB

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  1. ##################
  2. # Performance Model Version
  3. 45
  4. ####################
  5. # COMBs
  6. # number of combinations
  7. 9
  8. ####################
  9. # COMB_1
  10. # number of types devices
  11. 1
  12. ####################
  13. # DEV_0
  14. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3)
  15. 1
  16. ####################
  17. # DEV_0
  18. # device id
  19. 3
  20. ####################
  21. # DEV_0
  22. # number of cores
  23. 1
  24. ##########
  25. # number of implementations
  26. 1
  27. #####
  28. # Model for cuda3_impl0 (Comb1)
  29. # number of entries
  30. 3
  31. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  32. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  33. # a b c
  34. nan nan nan
  35. # not multiple-regression-base
  36. 0
  37. # hash size flops mean (us) dev (us) sum sum2 n
  38. 24c84a50 22118400 0.000000e+00 5.901996e+03 2.140574e+02 2.574451e+07 1.521439e+11 4362
  39. f0ac7beb 9830400 0.000000e+00 1.855425e+03 1.035707e+02 7.464374e+06 1.389274e+10 4023
  40. d46431bb 2457600 0.000000e+00 2.667843e+02 3.133790e+01 9.321442e+05 2.521128e+08 3494
  41. ####################
  42. # COMB_0
  43. # number of types devices
  44. 1
  45. ####################
  46. # DEV_0
  47. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3)
  48. 1
  49. ####################
  50. # DEV_0
  51. # device id
  52. 4
  53. ####################
  54. # DEV_0
  55. # number of cores
  56. 1
  57. ##########
  58. # number of implementations
  59. 1
  60. #####
  61. # Model for cuda4_impl0 (Comb0)
  62. # number of entries
  63. 3
  64. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  65. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  66. # a b c
  67. nan nan nan
  68. # not multiple-regression-base
  69. 0
  70. # hash size flops mean (us) dev (us) sum sum2 n
  71. 24c84a50 22118400 0.000000e+00 5.924812e+03 2.030546e+02 2.715934e+07 1.611030e+11 4584
  72. f0ac7beb 9830400 0.000000e+00 1.850857e+03 1.138114e+02 6.774137e+06 1.258537e+10 3660
  73. d46431bb 2457600 0.000000e+00 2.743267e+02 3.237528e+01 7.903352e+05 2.198298e+08 2881
  74. ####################
  75. # COMB_4
  76. # number of types devices
  77. 1
  78. ####################
  79. # DEV_0
  80. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3)
  81. 1
  82. ####################
  83. # DEV_0
  84. # device id
  85. 0
  86. ####################
  87. # DEV_0
  88. # number of cores
  89. 1
  90. ##########
  91. # number of implementations
  92. 1
  93. #####
  94. # Model for cuda0_impl0 (Comb4)
  95. # number of entries
  96. 3
  97. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  98. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  99. # a b c
  100. nan nan nan
  101. # not multiple-regression-base
  102. 0
  103. # hash size flops mean (us) dev (us) sum sum2 n
  104. 24c84a50 22118400 0.000000e+00 5.905959e+03 2.324106e+02 2.885061e+07 1.706544e+11 4885
  105. f0ac7beb 9830400 0.000000e+00 1.844033e+03 9.904039e+01 7.516278e+06 1.390024e+10 4076
  106. d46431bb 2457600 0.000000e+00 2.662813e+02 2.651200e+01 1.098144e+06 2.953140e+08 4124
  107. ####################
  108. # COMB_5
  109. # number of types devices
  110. 1
  111. ####################
  112. # DEV_0
  113. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3)
  114. 1
  115. ####################
  116. # DEV_0
  117. # device id
  118. 2
  119. ####################
  120. # DEV_0
  121. # number of cores
  122. 1
  123. ##########
  124. # number of implementations
  125. 1
  126. #####
  127. # Model for cuda2_impl0 (Comb5)
  128. # number of entries
  129. 3
  130. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  131. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  132. # a b c
  133. nan nan nan
  134. # not multiple-regression-base
  135. 0
  136. # hash size flops mean (us) dev (us) sum sum2 n
  137. 24c84a50 22118400 0.000000e+00 5.905860e+03 2.088868e+02 2.619840e+07 1.549176e+11 4436
  138. f0ac7beb 9830400 0.000000e+00 1.843182e+03 9.714398e+01 7.671323e+06 1.417892e+10 4162
  139. d46431bb 2457600 0.000000e+00 2.666213e+02 3.154593e+01 1.003829e+06 2.713890e+08 3765
  140. ####################
  141. # COMB_2
  142. # number of types devices
  143. 1
  144. ####################
  145. # DEV_0
  146. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3)
  147. 1
  148. ####################
  149. # DEV_0
  150. # device id
  151. 1
  152. ####################
  153. # DEV_0
  154. # number of cores
  155. 1
  156. ##########
  157. # number of implementations
  158. 1
  159. #####
  160. # Model for cuda1_impl0 (Comb2)
  161. # number of entries
  162. 3
  163. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  164. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  165. # a b c
  166. nan nan nan
  167. # not multiple-regression-base
  168. 0
  169. # hash size flops mean (us) dev (us) sum sum2 n
  170. 24c84a50 22118400 0.000000e+00 5.916743e+03 2.291447e+02 2.686793e+07 1.592091e+11 4541
  171. f0ac7beb 9830400 0.000000e+00 1.837574e+03 9.255327e+01 7.197777e+06 1.326000e+10 3917
  172. d46431bb 2457600 0.000000e+00 2.645367e+02 2.904285e+01 1.078252e+06 2.886751e+08 4076
  173. ####################
  174. # COMB_8
  175. # number of types devices
  176. 1
  177. ####################
  178. # DEV_0
  179. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3)
  180. 0
  181. ####################
  182. # DEV_0
  183. # device id
  184. 0
  185. ####################
  186. # DEV_0
  187. # number of cores
  188. 1
  189. ##########
  190. # number of implementations
  191. 1
  192. #####
  193. # Model for cpu0_impl0 (Comb8)
  194. # number of entries
  195. 3
  196. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  197. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  198. # a b c
  199. nan nan nan
  200. # not multiple-regression-base
  201. 0
  202. # hash size flops mean (us) dev (us) sum sum2 n
  203. 24c84a50 22118400 0.000000e+00 1.776444e+05 1.603881e+03 1.085407e+08 1.928322e+13 611
  204. f0ac7beb 9830400 0.000000e+00 5.438487e+04 1.553469e+03 1.598915e+07 8.702776e+11 294
  205. d46431bb 2457600 0.000000e+00 6.892168e+03 1.879454e+02 4.218007e+06 2.909283e+10 612
  206. ####################
  207. # COMB_6
  208. # number of types devices
  209. 1
  210. ####################
  211. # DEV_0
  212. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3)
  213. 1
  214. ####################
  215. # DEV_0
  216. # device id
  217. 6
  218. ####################
  219. # DEV_0
  220. # number of cores
  221. 1
  222. ##########
  223. # number of implementations
  224. 1
  225. #####
  226. # Model for cuda6_impl0 (Comb6)
  227. # number of entries
  228. 3
  229. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  230. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  231. # a b c
  232. nan nan nan
  233. # not multiple-regression-base
  234. 0
  235. # hash size flops mean (us) dev (us) sum sum2 n
  236. 24c84a50 22118400 0.000000e+00 5.908798e+03 2.191022e+02 2.432652e+07 1.439381e+11 4117
  237. f0ac7beb 9830400 0.000000e+00 1.870298e+03 1.158137e+02 6.306645e+06 1.184053e+10 3372
  238. d46431bb 2457600 0.000000e+00 2.622005e+02 3.221213e+01 7.630036e+05 2.030794e+08 2910
  239. ####################
  240. # COMB_7
  241. # number of types devices
  242. 1
  243. ####################
  244. # DEV_0
  245. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3)
  246. 1
  247. ####################
  248. # DEV_0
  249. # device id
  250. 5
  251. ####################
  252. # DEV_0
  253. # number of cores
  254. 1
  255. ##########
  256. # number of implementations
  257. 1
  258. #####
  259. # Model for cuda5_impl0 (Comb7)
  260. # number of entries
  261. 3
  262. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  263. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  264. # a b c
  265. # not multiple-regression-base
  266. 0
  267. nan nan nan
  268. # hash size flops mean (us) dev (us) sum sum2 n
  269. 24c84a50 22118400 0.000000e+00 5.908890e+03 2.133901e+02 2.731089e+07 1.615875e+11 4622
  270. f0ac7beb 9830400 0.000000e+00 1.853662e+03 1.234628e+02 6.493379e+06 1.208993e+10 3503
  271. d46431bb 2457600 0.000000e+00 2.672063e+02 3.249622e+01 7.262666e+05 1.969332e+08 2718
  272. ####################
  273. # COMB_3
  274. # number of types devices
  275. 1
  276. ####################
  277. # DEV_0
  278. # device type (CPU - 0, CUDA - 1, OPENCL - 2, MIC - 3)
  279. 1
  280. ####################
  281. # DEV_0
  282. # device id
  283. 7
  284. ####################
  285. # DEV_0
  286. # number of cores
  287. 1
  288. ##########
  289. # number of implementations
  290. 1
  291. #####
  292. # Model for cuda7_impl0 (Comb3)
  293. # number of entries
  294. 3
  295. # sumlnx sumlnx2 sumlny sumlnxlny alpha beta n minx maxx
  296. 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 nan nan 0 0 0
  297. # a b c
  298. nan nan nan
  299. # not multiple-regression-base
  300. 0
  301. # hash size flops mean (us) dev (us) sum sum2 n
  302. 24c84a50 22118400 0.000000e+00 5.908429e+03 2.149126e+02 2.371053e+07 1.402773e+11 4013
  303. f0ac7beb 9830400 0.000000e+00 1.855601e+03 1.161756e+02 6.509447e+06 1.212628e+10 3508
  304. d46431bb 2457600 0.000000e+00 2.697690e+02 3.186509e+01 7.013994e+05 1.918558e+08 2600