#include "stdsimheader.h" #include "StreamFMAKernel.h" namespace maxcompilersim { StreamFMAKernel::StreamFMAKernel(const std::string &instance_name) : ManagerBlockSync(instance_name), KernelManagerBlockSync(instance_name, 10, 2, 0, 0, "",1) , c_hw_fix_1_0_uns_bits((HWOffsetFix<1,0,UNSIGNED>(varint_u<1>(0x0l)))) , c_hw_fix_32_0_sgn_undef((HWOffsetFix<32,0,TWOSCOMPLEMENT>())) , c_hw_fix_1_0_uns_bits_1((HWOffsetFix<1,0,UNSIGNED>(varint_u<1>(0x1l)))) , c_hw_fix_49_0_uns_bits((HWOffsetFix<49,0,UNSIGNED>(varint_u<49>(0x1000000000000l)))) , c_hw_fix_49_0_uns_bits_1((HWOffsetFix<49,0,UNSIGNED>(varint_u<49>(0x0000000000000l)))) , c_hw_fix_49_0_uns_bits_2((HWOffsetFix<49,0,UNSIGNED>(varint_u<49>(0x0000000000001l)))) { { // Node ID: 8 (NodeInputMappedReg) registerMappedRegister("io_output_force_disabled", Data(1)); } { // Node ID: 0 (NodeInputMappedReg) registerMappedRegister("io_a_force_disabled", Data(1)); } { // Node ID: 2 (NodeInput) m_a = registerInput("a",0,5); } { // Node ID: 3 (NodeInputMappedReg) registerMappedRegister("io_b_force_disabled", Data(1)); } { // Node ID: 5 (NodeInput) m_b = registerInput("b",1,5); } { // Node ID: 11 (NodeOutput) m_output = registerOutput("output",0 ); } { // Node ID: 16 (NodeConstantRawBits) id16out_value = (c_hw_fix_1_0_uns_bits_1); } { // Node ID: 26 (NodeConstantRawBits) id26out_value = (c_hw_fix_1_0_uns_bits_1); } { // Node ID: 13 (NodeConstantRawBits) id13out_value = (c_hw_fix_49_0_uns_bits); } { // Node ID: 17 (NodeOutputMappedReg) registerMappedRegister("current_run_cycle_count", Data(48), true); } { // Node ID: 25 (NodeConstantRawBits) id25out_value = (c_hw_fix_1_0_uns_bits_1); } { // Node ID: 19 (NodeConstantRawBits) id19out_value = (c_hw_fix_49_0_uns_bits); } { // Node ID: 22 (NodeInputMappedReg) registerMappedRegister("run_cycle_count", Data(48)); } } void StreamFMAKernel::resetComputation() { resetComputationAfterFlush(); } void StreamFMAKernel::resetComputationAfterFlush() { { // Node ID: 8 (NodeInputMappedReg) id8out_io_output_force_disabled = getMappedRegValue >("io_output_force_disabled"); } { // Node ID: 0 (NodeInputMappedReg) id0out_io_a_force_disabled = getMappedRegValue >("io_a_force_disabled"); } { // Node ID: 2 (NodeInput) (id2st_read_next_cycle) = (c_hw_fix_1_0_uns_bits); (id2st_last_read_value) = (c_hw_fix_32_0_sgn_undef); } { // Node ID: 3 (NodeInputMappedReg) id3out_io_b_force_disabled = getMappedRegValue >("io_b_force_disabled"); } { // Node ID: 5 (NodeInput) (id5st_read_next_cycle) = (c_hw_fix_1_0_uns_bits); (id5st_last_read_value) = (c_hw_fix_32_0_sgn_undef); } { // Node ID: 14 (NodeCounter) (id14st_count) = (c_hw_fix_49_0_uns_bits_1); } { // Node ID: 20 (NodeCounter) (id20st_count) = (c_hw_fix_49_0_uns_bits_1); } { // Node ID: 22 (NodeInputMappedReg) id22out_run_cycle_count = getMappedRegValue >("run_cycle_count"); } } void StreamFMAKernel::updateState() { { // Node ID: 8 (NodeInputMappedReg) id8out_io_output_force_disabled = getMappedRegValue >("io_output_force_disabled"); } { // Node ID: 0 (NodeInputMappedReg) id0out_io_a_force_disabled = getMappedRegValue >("io_a_force_disabled"); } { // Node ID: 3 (NodeInputMappedReg) id3out_io_b_force_disabled = getMappedRegValue >("io_b_force_disabled"); } { // Node ID: 22 (NodeInputMappedReg) id22out_run_cycle_count = getMappedRegValue >("run_cycle_count"); } } void StreamFMAKernel::preExecute() { { // Node ID: 2 (NodeInput) if(((needsToReadInput(m_a))&(((getFlushLevel())<((4l)+(5)))|(!(isFlushingActive()))))) { (id2st_last_read_value) = (readInput >(m_a)); } id2out_data = (id2st_last_read_value); } { // Node ID: 5 (NodeInput) if(((needsToReadInput(m_b))&(((getFlushLevel())<((4l)+(5)))|(!(isFlushingActive()))))) { (id5st_last_read_value) = (readInput >(m_b)); } id5out_data = (id5st_last_read_value); } } void StreamFMAKernel::runComputationCycle() { if (m_mappedElementsChanged) { m_mappedElementsChanged = false; updateState(); std::cout << "StreamFMAKernel: Mapped Elements Changed: Reloaded" << std::endl; } preExecute(); execute0(); } int StreamFMAKernel::getFlushLevelStart() { return ((1l)+(3l)); } }