digraph manager_compiler_graph { StreamFMAKernel[shape=plaintext, label=<

a
clk=STREAM (100.0MHz)
width=32
PULL el=1 ael=2

b
clk=STREAM (100.0MHz)
width=32
PULL el=1 ael=2

Kernel : StreamFMAKernel

output
clk=STREAM (100.0MHz)
width=32
PUSH 5

>]; a[shape=plaintext, label=<

PCIe_From_Host : a

a
clk=PCIE (125.0MHz)
width=128
PUSH 2

>]; b[shape=plaintext, label=<

PCIe_From_Host : b

b
clk=PCIE (125.0MHz)
width=128
PUSH 2

>]; output[shape=plaintext, label=<

output
clk=PCIE (125.0MHz)
width=128
PUSH 1

PCIe_To_Host : output

>]; Stream_1[shape=plaintext, label=<

input
clk=PCIE (125.0MHz)
width=128
PULL el=1

DualAspectMux : Stream_1

output
clk=PCIE (125.0MHz)
width=32
PUSH 2

>]; Stream_4[shape=plaintext, label=<

input
clk=PCIE (125.0MHz)
width=128
PULL el=1

DualAspectMux : Stream_4

output
clk=PCIE (125.0MHz)
width=32
PUSH 2

>]; Stream_8[shape=plaintext, label=<

input
clk=PCIE (125.0MHz)
width=32
PULL el=1

DualAspectReg : Stream_8

output
clk=PCIE (125.0MHz)
width=128
PULL el=1

>]; a -> Stream_1 [headport="input" tailport="a" label="{D{data:1}}"] b -> Stream_4 [headport="input" tailport="b" label="{D{data:1}}"] StreamFMAKernel -> Stream_8 [headport="input" tailport="output" label="{D{data:1}}"] Stream_1 -> StreamFMAKernel [headport="a" tailport="output" label="{D{data:1}}"] Stream_4 -> StreamFMAKernel [headport="b" tailport="output" label="{D{data:1}}"] Stream_8 -> output [headport="output" tailport="output" label="{D{data:1}}"] }