digraph manager_compiler_graph { StreamFMAKernel[shape=plaintext, label=<
inAT1
clk=STREAM (100.0MHz)
width=32
PULL el=1 ael=2		inBT1
clk=STREAM (100.0MHz)
width=32
PULL el=1 ael=2		inAT2
clk=STREAM (100.0MHz)
width=32
PULL el=1 ael=2		inBT2
clk=STREAM (100.0MHz)
width=32
PULL el=1 ael=2		inAT3
clk=STREAM (100.0MHz)
width=32
PULL el=1 ael=2		inBT3
clk=STREAM (100.0MHz)
width=32
PULL el=1 ael=2
Kernel : StreamFMAKernel
oDataT1
clk=STREAM (100.0MHz)
width=32
PUSH 5		oDataT2
clk=STREAM (100.0MHz)
width=32
PUSH 5		oDataT3
clk=STREAM (100.0MHz)
width=32
PUSH 5
>]; inAT1[shape=plaintext, label=<
PCIe_From_Host : inAT1
inAT1
clk=PCIE (125.0MHz)
width=128
PUSH 2
>]; inBT1[shape=plaintext, label=<
PCIe_From_Host : inBT1
inBT1
clk=PCIE (125.0MHz)
width=128
PUSH 2
>]; oDataT3[shape=plaintext, label=<
oDataT3
clk=PCIE (125.0MHz)
width=128
PUSH 1
PCIe_To_Host : oDataT3
>]; MemoryControllerPro0[shape=plaintext, label=<
read_stream_maxj_a
clk=MemoryControllerPro0_clk (272.5MHz)
width=512
PULL el=1 ael=3		read_stream_maxj_b
clk=MemoryControllerPro0_clk (272.5MHz)
width=512
PULL el=1 ael=3		read_stream_maxj_c
clk=MemoryControllerPro0_clk (272.5MHz)
width=512
PULL el=1 ael=3		read_command_0
clk=MemoryControllerPro0_clk (272.5MHz)
width=64
PUSH 8		read_command_1
clk=MemoryControllerPro0_clk (272.5MHz)
width=64
PUSH 8		read_command_2
clk=MemoryControllerPro0_clk (272.5MHz)
width=64
PUSH 8		read_command_3
clk=MemoryControllerPro0_clk (272.5MHz)
width=64
PUSH 8		write_0
clk=STREAM (100.0MHz)
width=1536
PUSH 8		write_1
clk=STREAM (100.0MHz)
width=1536
PUSH 8		write_command_0
clk=MemoryControllerPro0_clk (272.5MHz)
width=64
PUSH 8		write_command_1
clk=MemoryControllerPro0_clk (272.5MHz)
width=64
PUSH 8
ManagerStateMachine_MemoryControllerPro0 : MemoryControllerPro0
read_0
clk=STREAM (100.0MHz)
width=1536
PULL el=1 ael=8		read_1
clk=STREAM (100.0MHz)
width=1536
PULL el=1 ael=8		read_2
clk=STREAM (100.0MHz)
width=1536
PULL el=1 ael=8		read_3
clk=STREAM (100.0MHz)
width=1536
PULL el=1 ael=8		Tag_Out
clk=MemoryControllerPro0_clk (272.5MHz)
width=1
PUSH 1		cmd_stream_maxj_a
clk=MemoryControllerPro0_clk (272.5MHz)
width=544
PUSH 3		cmd_stream_maxj_b
clk=MemoryControllerPro0_clk (272.5MHz)
width=544
PUSH 3		cmd_stream_maxj_c
clk=MemoryControllerPro0_clk (272.5MHz)
width=544
PUSH 3
>]; MemoryControllerPro0_IntSource[shape=plaintext, label=<
Tag_In
clk=(clk)
width=1
PUSH 1
MemoryInterruptSource : MemoryControllerPro0_IntSource
>]; MemoryControllerInterface_b[shape=plaintext, label=<
cmd_stream_maxj
clk=DDR_CLK_b (266.6MHz)
width=544
PULL el=1
MemoryControllerInterface_b : MemoryControllerInterface_b
read_stream_maxj
clk=DDR_CLK_b (266.6MHz)
width=512
PUSH 1
>]; MemoryControllerInterface_a[shape=plaintext, label=<
cmd_stream_maxj
clk=DDR_CLK_a (266.6MHz)
width=544
PULL el=1
MemoryControllerInterface_a : MemoryControllerInterface_a
read_stream_maxj
clk=DDR_CLK_a (266.6MHz)
width=512
PUSH 1
>]; MemoryControllerInterface_c[shape=plaintext, label=<
cmd_stream_maxj
clk=DDR_CLK_c (266.6MHz)
width=544
PULL el=1
MemoryControllerInterface_c : MemoryControllerInterface_c
read_stream_maxj
clk=DDR_CLK_c (266.6MHz)
width=512
PUSH 1
>]; addrgen_cmd_MemoryControllerPro0_inAT2[shape=plaintext, label=<
ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_inAT2 : addrgen_cmd_MemoryControllerPro0_inAT2
cgen_out_0
clk=STREAM (100.0MHz)
width=64
PUSH 1
>]; addrgen_cmd_MemoryControllerPro0_inBT2[shape=plaintext, label=<
ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_inBT2 : addrgen_cmd_MemoryControllerPro0_inBT2
cgen_out_0
clk=STREAM (100.0MHz)
width=64
PUSH 1
>]; addrgen_cmd_MemoryControllerPro0_inAT3[shape=plaintext, label=<
ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_inAT3 : addrgen_cmd_MemoryControllerPro0_inAT3
cgen_out_0
clk=STREAM (100.0MHz)
width=64
PUSH 1
>]; addrgen_cmd_MemoryControllerPro0_inBT3[shape=plaintext, label=<
ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_inBT3 : addrgen_cmd_MemoryControllerPro0_inBT3
cgen_out_0
clk=STREAM (100.0MHz)
width=64
PUSH 1
>]; addrgen_cmd_MemoryControllerPro0_oDataT1[shape=plaintext, label=<
ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_oDataT1 : addrgen_cmd_MemoryControllerPro0_oDataT1
cgen_out_0
clk=STREAM (100.0MHz)
width=64
PUSH 1
>]; addrgen_cmd_MemoryControllerPro0_oDataT2[shape=plaintext, label=<
ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_oDataT2 : addrgen_cmd_MemoryControllerPro0_oDataT2
cgen_out_0
clk=STREAM (100.0MHz)
width=64
PUSH 1
>]; Stream_34_pipeline_4[shape=plaintext, label=<
input
clk=DDR_CLK_a (266.6MHz)
width=(width)
PUSH [StallTo]input
Stream_34_pipeline : Stream_34_pipeline_4
output
clk=DDR_CLK_a (266.6MHz)
width=(width)
PUSH ([StallTo]input + 8)
>]; Stream_29_pipeline_4[shape=plaintext, label=<
input
clk=DDR_CLK_b (266.6MHz)
width=(width)
PUSH [StallTo]input
Stream_29_pipeline : Stream_29_pipeline_4
output
clk=DDR_CLK_b (266.6MHz)
width=(width)
PUSH ([StallTo]input + 8)
>]; Stream_39_pipeline_4[shape=plaintext, label=<
input
clk=DDR_CLK_c (266.6MHz)
width=(width)
PUSH [StallTo]input
Stream_39_pipeline : Stream_39_pipeline_4
output
clk=DDR_CLK_c (266.6MHz)
width=(width)
PUSH ([StallTo]input + 8)
>]; Stream_28_pipeline_4[shape=plaintext, label=<
input
clk=MemoryControllerPro0_clk (272.5MHz)
width=(width)
PUSH [StallTo]input
Stream_28_pipeline : Stream_28_pipeline_4
output
clk=MemoryControllerPro0_clk (272.5MHz)
width=(width)
PUSH ([StallTo]input + 8)
>]; Stream_33_pipeline_4[shape=plaintext, label=<
input
clk=MemoryControllerPro0_clk (272.5MHz)
width=(width)
PUSH [StallTo]input
Stream_33_pipeline : Stream_33_pipeline_4
output
clk=MemoryControllerPro0_clk (272.5MHz)
width=(width)
PUSH ([StallTo]input + 8)
>]; Stream_38_pipeline_4[shape=plaintext, label=<
input
clk=MemoryControllerPro0_clk (272.5MHz)
width=(width)
PUSH [StallTo]input
Stream_38_pipeline : Stream_38_pipeline_4
output
clk=MemoryControllerPro0_clk (272.5MHz)
width=(width)
PUSH ([StallTo]input + 8)
>]; inAT1 -> StreamFMAKernel [headport="inAT1" tailport="inAT1" label="{D{data:1}}"] inBT1 -> StreamFMAKernel [headport="inBT1" tailport="inBT1" label="{D{data:1}}"] StreamFMAKernel -> MemoryControllerPro0 [headport="write_0" tailport="oDataT1" label="{D{data:1}}"] StreamFMAKernel -> MemoryControllerPro0 [headport="write_1" tailport="oDataT2" label="{D{data:1}}"] StreamFMAKernel -> oDataT3 [headport="oDataT3" tailport="oDataT3" label="{D{data:1}}"] MemoryControllerPro0 -> MemoryControllerPro0_IntSource [headport="Tag_In" tailport="Tag_Out" label="{D{data:1}}"] MemoryControllerPro0 -> Stream_28_pipeline_4 [headport="input" tailport="cmd_stream_maxj_b" label="{D{data:1}}"] MemoryControllerInterface_b -> Stream_29_pipeline_4 [headport="input" tailport="read_stream_maxj" label="{D{data:1}}"] MemoryControllerPro0 -> Stream_33_pipeline_4 [headport="input" tailport="cmd_stream_maxj_a" label="{D{data:1}}"] MemoryControllerInterface_a -> Stream_34_pipeline_4 [headport="input" tailport="read_stream_maxj" label="{D{data:1}}"] MemoryControllerPro0 -> Stream_38_pipeline_4 [headport="input" tailport="cmd_stream_maxj_c" label="{D{data:1}}"] MemoryControllerInterface_c -> Stream_39_pipeline_4 [headport="input" tailport="read_stream_maxj" label="{D{data:1}}"] addrgen_cmd_MemoryControllerPro0_inAT2 -> MemoryControllerPro0 [headport="read_command_0" tailport="cgen_out_0" label="{D{data:1}}"] MemoryControllerPro0 -> StreamFMAKernel [headport="inAT2" tailport="read_0" label="{D{data:1}}"] addrgen_cmd_MemoryControllerPro0_inBT2 -> MemoryControllerPro0 [headport="read_command_1" tailport="cgen_out_0" label="{D{data:1}}"] MemoryControllerPro0 -> StreamFMAKernel [headport="inBT2" tailport="read_1" label="{D{data:1}}"] addrgen_cmd_MemoryControllerPro0_inAT3 -> MemoryControllerPro0 [headport="read_command_2" tailport="cgen_out_0" label="{D{data:1}}"] MemoryControllerPro0 -> StreamFMAKernel [headport="inAT3" tailport="read_2" label="{D{data:1}}"] addrgen_cmd_MemoryControllerPro0_inBT3 -> MemoryControllerPro0 [headport="read_command_3" tailport="cgen_out_0" label="{D{data:1}}"] MemoryControllerPro0 -> StreamFMAKernel [headport="inBT3" tailport="read_3" label="{D{data:1}}"] addrgen_cmd_MemoryControllerPro0_oDataT1 -> MemoryControllerPro0 [headport="write_command_0" tailport="cgen_out_0" label="{D{data:1}}"] addrgen_cmd_MemoryControllerPro0_oDataT2 -> MemoryControllerPro0 [headport="write_command_1" tailport="cgen_out_0" label="{D{data:1}}"] Stream_34_pipeline_4 -> MemoryControllerPro0 [headport="read_stream_maxj_a" tailport="output" label="{D{data:1}}"] Stream_29_pipeline_4 -> MemoryControllerPro0 [headport="read_stream_maxj_b" tailport="output" label="{D{data:1}}"] Stream_39_pipeline_4 -> MemoryControllerPro0 [headport="read_stream_maxj_c" tailport="output" label="{D{data:1}}"] Stream_28_pipeline_4 -> MemoryControllerInterface_b [headport="cmd_stream_maxj" tailport="output" label="{D{data:1}}"] Stream_33_pipeline_4 -> MemoryControllerInterface_a [headport="cmd_stream_maxj" tailport="output" label="{D{data:1}}"] Stream_38_pipeline_4 -> MemoryControllerInterface_c [headport="cmd_stream_maxj" tailport="output" label="{D{data:1}}"] }