package fpga;

import com.maxeler.maxcompiler.v2.kernelcompiler.Kernel;
import com.maxeler.maxcompiler.v2.kernelcompiler.KernelParameters;
import com.maxeler.maxcompiler.v2.kernelcompiler.types.base.DFEType;
import com.maxeler.maxcompiler.v2.kernelcompiler.types.base.DFEVar;

class StreamFMAKernel extends Kernel
{
	private static final DFEType type = dfeInt(32);

	protected StreamFMAKernel(KernelParameters parameters)
	{
		super(parameters);

                DFEVar inAT1 = io.input("inAT1", type);
                DFEVar inBT1 = io.input("inBT1", type);
                DFEVar oDataT1;

                DFEVar inAT2 = io.input("inAT2", type);
                DFEVar inBT2 = io.input("inBT2", type);
                DFEVar oDataT2;

                DFEVar inAT3 = io.input("inAT3", type);
                DFEVar inBT3 = io.input("inBT3", type);
                DFEVar oDataT3;

                oDataT1 = inAT1+inBT1;
                oDataT2 = inAT2*inBT2;
                oDataT3 = inAT3+inBT3;

                io.output("oDataT1", oDataT1, type);
                io.output("oDataT2", oDataT2, type);
                io.output("oDataT3", oDataT3, type);
	}
}