drop spurious files

tests/.gitignore

@@ -1 +1,2 @@
 /.deps
+StreamFMA_MAX5C_DFE_SIM

tests/StreamFMA_MAX5C_DFE_SIM/_init.conf

@@ -1,62 +0,0 @@
-#
-#Tue Jan 28 16:01:03 CET 2020
-build.quartus_version=13.1
-photon.verbose_simulation=true
-xdl.cluster_tags=linux
-xst.ram_usage=4096
-xst.cluster_tags=linux
-ngcbuild.cluster_tags=linux
-build.arbitrated_core_cache=
-xdl.command=xdl
-build.datestamp_builds_format=dd-MM-yy
-simulation.compile.max_optimization_level=2
-maxfile.ram_usage=5120
-ngdbuild.command=ngdbuild
-mapper.command=map
-maxfile.cluster_tags=linux
-user_friendly_stack_traces=true
-buildresource.medium_build_factor=80
-release_mode=true
-buildresource.small_build_factor=50
-buildresource.abort_when_overmapped_dsps=true
-trce.ram_usage=8192
-bitgen.command=bitgen
-build.root_dir=
-buildresource.autoresize=true
-ngcbuild.command=ngcbuild
-simulation.compile.precompiled_header=1
-xdl.ram_usage=4096
-simulation.compile.explicit_template_instantiation=1
-ngdbuild.ram_usage=4096
-buildresource.abort_when_overmapped_bram=true
-par.command=par
-coregen.command=coregen
-ngcbuild.ram_usage=4096
-build.print_run_job_hashes=false
-photon.draw_control_nodes=true
-xst.command=ulimit -s unlimited && xst
-vsim.retry_delay=60
-ngdbuild.cluster_tags=linux
-buildresource.abort_when_overmapped_ffs=false
-build.ise_version=13.3
-maxfile.command=/opt/Software/maxeler/maxcompiler-2018.3.1/bin/maxfilestitch
-trce.command=trce
-build.verbose_output=false
-vsim.retries=5
-mapper.ram_usage=8192
-simulation.compile.parallelism=2
-build.datestamp_builds=false
-simulation.compile.generate_debug_info=0
-buildresource.small_build_is=45000
-buildresource.medium_build_is=100000
-dot.ram_usage=2048
-par.cluster_tags=linux;longrun
-par.ram_usage=8192
-photon.coloured_graph_lines=true
-vsim.command=vsim
-bitgen.ram_usage=5120
-photon.draw_groups=false
-build.enable_source_backup=true
-modelsim.ram_usage=1024
-trce.cluster_tags=linux
-mapper.cluster_tags=linux;longrun

tests/StreamFMA_MAX5C_DFE_SIM/results/StreamFMA-StreamFMAKernel-final-simulation.pxg

@@ -1 +0,0 @@
-../scratch/StreamFMA-StreamFMAKernel-final-simulation.pxg

tests/StreamFMA_MAX5C_DFE_SIM/results/StreamFMA-StreamFMAKernel-original.pxg

@@ -1 +0,0 @@
-../scratch/StreamFMA-StreamFMAKernel-original.pxg

tests/StreamFMA_MAX5C_DFE_SIM/results/StreamFMA.h

@@ -1 +0,0 @@
-../scratch/StreamFMA.h

tests/StreamFMA_MAX5C_DFE_SIM/results/StreamFMA.max

@@ -1 +0,0 @@
-../scratch/StreamFMA.max

tests/StreamFMA_MAX5C_DFE_SIM/results/StreamFMA.xml

@@ -1 +0,0 @@
-../scratch/StreamFMA.xml

tests/StreamFMA_MAX5C_DFE_SIM/results/StreamFMAKernel_Configuration.txt

@@ -1 +0,0 @@
-../scratch/StreamFMAKernel_Configuration.txt

tests/StreamFMA_MAX5C_DFE_SIM/results/StreamFMAKernel_NodeDiary.txt

@@ -1 +0,0 @@
-../scratch/StreamFMAKernel_NodeDiary.txt

tests/StreamFMA_MAX5C_DFE_SIM/scratch/Manager_StreamFMA.graphs

@@ -1,16 +0,0 @@
-Tue Jan 28 16:01:07 CET 2020
-Manager_StreamFMA
-orig
-Manager_StreamFMA_orig.dot
-pipelining
-Manager_StreamFMA_pipelining.dot
-schedstall
-Manager_StreamFMA_schedstall.dot
-clockwidth
-Manager_StreamFMA_clockwidth.dot
-dualaspect
-Manager_StreamFMA_dualaspect.dot
-pullpush
-Manager_StreamFMA_pullpush.dot
-final
-Manager_StreamFMA_final.dot

tests/StreamFMA_MAX5C_DFE_SIM/scratch/Manager_StreamFMA_Final.mxg

@@ -1,495 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" ?>
-<ManagerGraph version="2018.3.1" design_name="Manager_StreamFMA" compilation_phase="Final" hardwareBuild="false">
-	<Node id="61" instanceName="addrgen_cmd_MemoryControllerPro0_oDataT2" type="McpAddressGenerator">
-		<Output clock="STREAM" name="cgen_out_0" type="PUSH 1" width="64">
-			<Stream name="Stream_63" sink="193" />
-		</Output>
-	</Node>
-	<Node id="2" instanceName="inAT1" type="Input">
-		<Output clock="PCIE" name="inAT1" type="PUSH 2" width="128">
-			<Stream name="Stream_3" sink="137" />
-		</Output>
-	</Node>
-	<Node id="57" instanceName="addrgen_cmd_MemoryControllerPro0_oDataT1" type="McpAddressGenerator">
-		<Output clock="STREAM" name="cgen_out_0" type="PUSH 1" width="64">
-			<Stream name="Stream_59" sink="189" />
-		</Output>
-	</Node>
-	<Node id="45" instanceName="addrgen_cmd_MemoryControllerPro0_inBT2" type="McpAddressGenerator">
-		<Output clock="STREAM" name="cgen_out_0" type="PUSH 1" width="64">
-			<Stream name="Stream_47" sink="177" />
-		</Output>
-	</Node>
-	<Node id="5" instanceName="inBT1" type="Input">
-		<Output clock="PCIE" name="inBT1" type="PUSH 2" width="128">
-			<Stream name="Stream_6" sink="141" />
-		</Output>
-	</Node>
-	<Node id="49" instanceName="addrgen_cmd_MemoryControllerPro0_inAT3" type="McpAddressGenerator">
-		<Output clock="STREAM" name="cgen_out_0" type="PUSH 1" width="64">
-			<Stream name="Stream_51" sink="181" />
-		</Output>
-	</Node>
-	<Node id="53" instanceName="addrgen_cmd_MemoryControllerPro0_inBT3" type="McpAddressGenerator">
-		<Output clock="STREAM" name="cgen_out_0" type="PUSH 1" width="64">
-			<Stream name="Stream_55" sink="185" />
-		</Output>
-	</Node>
-	<Node id="41" instanceName="addrgen_cmd_MemoryControllerPro0_inAT2" type="McpAddressGenerator">
-		<Output clock="STREAM" name="cgen_out_0" type="PUSH 1" width="64">
-			<Stream name="Stream_43" sink="173" />
-		</Output>
-	</Node>
-	<Node id="189" instanceName="Stream_58" type="Fifo">
-		<Input clock="STREAM" name="input" type="PUSH 1" width="64">
-			<Stream name="Stream_190" source="57" />
-		</Input>
-		<Output clock="MemoryControllerPro0_clk" name="output" type="PUSH 8" width="64">
-			<Stream name="Stream_191" sink="22" />
-		</Output>
-	</Node>
-	<Node id="181" instanceName="Stream_50" type="Fifo">
-		<Input clock="STREAM" name="input" type="PUSH 1" width="64">
-			<Stream name="Stream_182" source="49" />
-		</Input>
-		<Output clock="MemoryControllerPro0_clk" name="output" type="PUSH 8" width="64">
-			<Stream name="Stream_183" sink="22" />
-		</Output>
-	</Node>
-	<Node id="173" instanceName="Stream_42" type="Fifo">
-		<Input clock="STREAM" name="input" type="PUSH 1" width="64">
-			<Stream name="Stream_174" source="41" />
-		</Input>
-		<Output clock="MemoryControllerPro0_clk" name="output" type="PUSH 8" width="64">
-			<Stream name="Stream_175" sink="22" />
-		</Output>
-	</Node>
-	<Node id="137" instanceName="Stream_98" type="Fifo">
-		<Input clock="PCIE" name="input" type="PUSH 2" width="128">
-			<Stream name="Stream_138" source="2" />
-		</Input>
-		<Output clock="PCIE" name="output" type="PULL el=1" width="128">
-			<Stream name="Stream_139" sink="97" />
-		</Output>
-	</Node>
-	<Node id="193" instanceName="Stream_62" type="Fifo">
-		<Input clock="STREAM" name="input" type="PUSH 1" width="64">
-			<Stream name="Stream_194" source="61" />
-		</Input>
-		<Output clock="MemoryControllerPro0_clk" name="output" type="PUSH 8" width="64">
-			<Stream name="Stream_195" sink="22" />
-		</Output>
-	</Node>
-	<Node id="185" instanceName="Stream_54" type="Fifo">
-		<Input clock="STREAM" name="input" type="PUSH 1" width="64">
-			<Stream name="Stream_186" source="53" />
-		</Input>
-		<Output clock="MemoryControllerPro0_clk" name="output" type="PUSH 8" width="64">
-			<Stream name="Stream_187" sink="22" />
-		</Output>
-	</Node>
-	<Node id="177" instanceName="Stream_46" type="Fifo">
-		<Input clock="STREAM" name="input" type="PUSH 1" width="64">
-			<Stream name="Stream_178" source="45" />
-		</Input>
-		<Output clock="MemoryControllerPro0_clk" name="output" type="PUSH 8" width="64">
-			<Stream name="Stream_179" sink="22" />
-		</Output>
-	</Node>
-	<Node id="141" instanceName="Stream_102" type="Fifo">
-		<Input clock="PCIE" name="input" type="PUSH 2" width="128">
-			<Stream name="Stream_142" source="5" />
-		</Input>
-		<Output clock="PCIE" name="output" type="PULL el=1" width="128">
-			<Stream name="Stream_143" sink="101" />
-		</Output>
-	</Node>
-	<Node id="101" instanceName="Stream_4" type="DualAspectMux">
-		<Input clock="PCIE" name="input" type="PULL el=1" width="128">
-			<Stream name="Stream_144" source="141" />
-		</Input>
-		<Output clock="PCIE" name="output" type="PUSH 2" width="32">
-			<Stream name="Stream_103" sink="201" />
-		</Output>
-	</Node>
-	<Node id="97" instanceName="Stream_1" type="DualAspectMux">
-		<Input clock="PCIE" name="input" type="PULL el=1" width="128">
-			<Stream name="Stream_140" source="137" />
-		</Input>
-		<Output clock="PCIE" name="output" type="PUSH 2" width="32">
-			<Stream name="Stream_99" sink="197" />
-		</Output>
-	</Node>
-	<Node id="201" instanceName="Stream_104" type="Fifo">
-		<Input clock="PCIE" name="input" type="PUSH 2" width="32">
-			<Stream name="Stream_202" source="101" />
-		</Input>
-		<Output clock="STREAM" name="output" type="PULL el=1 ael=2" width="32">
-			<Stream name="Stream_203" sink="0" />
-		</Output>
-	</Node>
-	<Node id="197" instanceName="Stream_100" type="Fifo">
-		<Input clock="PCIE" name="input" type="PUSH 2" width="32">
-			<Stream name="Stream_198" source="97" />
-		</Input>
-		<Output clock="STREAM" name="output" type="PULL el=1 ael=2" width="32">
-			<Stream name="Stream_199" sink="0" />
-		</Output>
-	</Node>
-	<Node id="129" instanceName="Stream_96" type="PullPushAdapter">
-		<Input clock="STREAM" name="input" type="PULL el=1" width="1536">
-			<Stream name="Stream_130" source="93" />
-		</Input>
-		<Output clock="STREAM" name="output" type="PUSH 1" width="1536">
-			<Stream name="Stream_131" sink="22" />
-		</Output>
-	</Node>
-	<Node id="77" instanceName="Stream_28_pipeline_4" type="Pipeline">
-		<Input clock="MemoryControllerPro0_clk" name="input" type="PUSH 3" width="544">
-			<Stream name="Stream_78" source="22" />
-		</Input>
-		<Output clock="MemoryControllerPro0_clk" name="output" type="PUSH 11" width="544">
-			<Stream name="Stream_79" sink="149" />
-		</Output>
-	</Node>
-	<Node id="149" instanceName="Stream_80" type="Fifo">
-		<Input clock="MemoryControllerPro0_clk" name="input" type="PUSH 11" width="544">
-			<Stream name="Stream_150" source="77" />
-		</Input>
-		<Output clock="DDR_CLK_b" name="output" type="PULL el=1" width="544">
-			<Stream name="Stream_151" sink="26" />
-		</Output>
-	</Node>
-	<Node id="26" instanceName="MemoryControllerInterface_b" type="Max5Mci">
-		<Input clock="DDR_CLK_b" name="cmd_stream_maxj" type="PULL el=1" width="544">
-			<Stream name="Stream_152" source="149" />
-		</Input>
-		<Output clock="DDR_CLK_b" name="read_stream_maxj" type="PUSH 1" width="512">
-			<Stream name="Stream_29" sink="69" />
-		</Output>
-	</Node>
-	<Node id="69" instanceName="Stream_29_pipeline_4" type="Pipeline">
-		<Input clock="DDR_CLK_b" name="input" type="PUSH 1" width="512">
-			<Stream name="Stream_70" source="26" />
-		</Input>
-		<Output clock="DDR_CLK_b" name="output" type="PUSH 9" width="512">
-			<Stream name="Stream_71" sink="165" />
-		</Output>
-	</Node>
-	<Node id="165" instanceName="Stream_72" type="Fifo">
-		<Input clock="DDR_CLK_b" name="input" type="PUSH 9" width="512">
-			<Stream name="Stream_166" source="69" />
-		</Input>
-		<Output clock="MemoryControllerPro0_clk" name="output" type="PULL el=1 ael=3" width="512">
-			<Stream name="Stream_167" sink="22" />
-		</Output>
-	</Node>
-	<Node id="153" instanceName="Stream_84" type="Fifo">
-		<Input clock="MemoryControllerPro0_clk" name="input" type="PUSH 11" width="544">
-			<Stream name="Stream_154" source="81" />
-		</Input>
-		<Output clock="DDR_CLK_a" name="output" type="PULL el=1" width="544">
-			<Stream name="Stream_155" sink="31" />
-		</Output>
-	</Node>
-	<Node id="31" instanceName="MemoryControllerInterface_a" type="Max5Mci">
-		<Input clock="DDR_CLK_a" name="cmd_stream_maxj" type="PULL el=1" width="544">
-			<Stream name="Stream_156" source="153" />
-		</Input>
-		<Output clock="DDR_CLK_a" name="read_stream_maxj" type="PUSH 1" width="512">
-			<Stream name="Stream_34" sink="65" />
-		</Output>
-	</Node>
-	<Node id="65" instanceName="Stream_34_pipeline_4" type="Pipeline">
-		<Input clock="DDR_CLK_a" name="input" type="PUSH 1" width="512">
-			<Stream name="Stream_66" source="31" />
-		</Input>
-		<Output clock="DDR_CLK_a" name="output" type="PUSH 9" width="512">
-			<Stream name="Stream_67" sink="161" />
-		</Output>
-	</Node>
-	<Node id="161" instanceName="Stream_68" type="Fifo">
-		<Input clock="DDR_CLK_a" name="input" type="PUSH 9" width="512">
-			<Stream name="Stream_162" source="65" />
-		</Input>
-		<Output clock="MemoryControllerPro0_clk" name="output" type="PULL el=1 ael=3" width="512">
-			<Stream name="Stream_163" sink="22" />
-		</Output>
-	</Node>
-	<Node id="157" instanceName="Stream_90" type="Fifo">
-		<Input clock="STREAM" name="input" type="PUSH 5" width="32">
-			<Stream name="Stream_158" source="0" />
-		</Input>
-		<Output clock="STREAM" name="output" type="PULL el=1" width="32">
-			<Stream name="Stream_159" sink="89" />
-		</Output>
-	</Node>
-	<Node id="89" instanceName="Stream_60" type="DualAspectReg">
-		<Input clock="STREAM" name="input" type="PULL el=1" width="32">
-			<Stream name="Stream_160" source="157" />
-		</Input>
-		<Output clock="STREAM" name="output" type="PULL el=1" width="1536">
-			<Stream name="Stream_91" sink="125" />
-		</Output>
-	</Node>
-	<Node id="125" instanceName="Stream_92" type="PullPushAdapter">
-		<Input clock="STREAM" name="input" type="PULL el=1" width="1536">
-			<Stream name="Stream_126" source="89" />
-		</Input>
-		<Output clock="STREAM" name="output" type="PUSH 1" width="1536">
-			<Stream name="Stream_127" sink="22" />
-		</Output>
-	</Node>
-	<Node id="105" instanceName="Stream_8" type="DualAspectMux">
-		<Input clock="STREAM" name="input" type="PULL el=1" width="1536">
-			<Stream name="Stream_106" source="22" />
-		</Input>
-		<Output clock="STREAM" name="output" type="PUSH 2" width="32">
-			<Stream name="Stream_107" sink="205" />
-		</Output>
-	</Node>
-	<Node id="205" instanceName="Stream_108" type="Fifo">
-		<Input clock="STREAM" name="input" type="PUSH 2" width="32">
-			<Stream name="Stream_206" source="105" />
-		</Input>
-		<Output clock="STREAM" name="output" type="PULL el=1 ael=2" width="32">
-			<Stream name="Stream_207" sink="0" />
-		</Output>
-	</Node>
-	<Node id="209" instanceName="Stream_112" type="Fifo">
-		<Input clock="STREAM" name="input" type="PUSH 2" width="32">
-			<Stream name="Stream_210" source="109" />
-		</Input>
-		<Output clock="STREAM" name="output" type="PULL el=1 ael=2" width="32">
-			<Stream name="Stream_211" sink="0" />
-		</Output>
-	</Node>
-	<Node id="133" instanceName="Stream_124" type="PullPushAdapter">
-		<Input clock="PCIE" name="input" type="PULL el=1" width="128">
-			<Stream name="Stream_134" source="121" />
-		</Input>
-		<Output clock="PCIE" name="output" type="PUSH 1" width="128">
-			<Stream name="Stream_135" sink="19" />
-		</Output>
-	</Node>
-	<Node id="19" instanceName="oDataT3" type="Output">
-		<Input clock="PCIE" name="oDataT3" type="PUSH 1" width="128">
-			<Stream name="Stream_136" source="133" />
-		</Input>
-	</Node>
-	<Node id="109" instanceName="Stream_10" type="DualAspectMux">
-		<Input clock="STREAM" name="input" type="PULL el=1" width="1536">
-			<Stream name="Stream_110" source="22" />
-		</Input>
-		<Output clock="STREAM" name="output" type="PUSH 2" width="32">
-			<Stream name="Stream_111" sink="209" />
-		</Output>
-	</Node>
-	<Node id="73" instanceName="Stream_39_pipeline_4" type="Pipeline">
-		<Input clock="DDR_CLK_c" name="input" type="PUSH 1" width="512">
-			<Stream name="Stream_74" source="36" />
-		</Input>
-		<Output clock="DDR_CLK_c" name="output" type="PUSH 9" width="512">
-			<Stream name="Stream_75" sink="169" />
-		</Output>
-	</Node>
-	<Node id="169" instanceName="Stream_76" type="Fifo">
-		<Input clock="DDR_CLK_c" name="input" type="PUSH 9" width="512">
-			<Stream name="Stream_170" source="73" />
-		</Input>
-		<Output clock="MemoryControllerPro0_clk" name="output" type="PULL el=1 ael=3" width="512">
-			<Stream name="Stream_171" sink="22" />
-		</Output>
-	</Node>
-	<Node id="22" instanceName="MemoryControllerPro0" type="MemoryControllerPro">
-		<Input clock="MemoryControllerPro0_clk" name="read_stream_maxj_a" type="PULL el=1 ael=3" width="512">
-			<Stream name="Stream_164" source="161" />
-		</Input>
-		<Input clock="MemoryControllerPro0_clk" name="read_stream_maxj_b" type="PULL el=1 ael=3" width="512">
-			<Stream name="Stream_168" source="165" />
-		</Input>
-		<Input clock="MemoryControllerPro0_clk" name="read_stream_maxj_c" type="PULL el=1 ael=3" width="512">
-			<Stream name="Stream_172" source="169" />
-		</Input>
-		<Input clock="MemoryControllerPro0_clk" name="read_command_0" type="PUSH 8" width="64">
-			<Stream name="Stream_176" source="173" />
-		</Input>
-		<Input clock="MemoryControllerPro0_clk" name="read_command_1" type="PUSH 8" width="64">
-			<Stream name="Stream_180" source="177" />
-		</Input>
-		<Input clock="MemoryControllerPro0_clk" name="read_command_2" type="PUSH 8" width="64">
-			<Stream name="Stream_184" source="181" />
-		</Input>
-		<Input clock="MemoryControllerPro0_clk" name="read_command_3" type="PUSH 8" width="64">
-			<Stream name="Stream_188" source="185" />
-		</Input>
-		<Input clock="STREAM" name="write_0" type="PUSH 8" width="1536">
-			<Stream name="Stream_128" source="125" />
-		</Input>
-		<Input clock="STREAM" name="write_1" type="PUSH 8" width="1536">
-			<Stream name="Stream_132" source="129" />
-		</Input>
-		<Input clock="MemoryControllerPro0_clk" name="write_command_0" type="PUSH 8" width="64">
-			<Stream name="Stream_192" source="189" />
-		</Input>
-		<Input clock="MemoryControllerPro0_clk" name="write_command_1" type="PUSH 8" width="64">
-			<Stream name="Stream_196" source="193" />
-		</Input>
-		<Output clock="STREAM" name="read_0" type="PULL el=1 ael=8" width="1536">
-			<Stream name="Stream_44" sink="105" />
-		</Output>
-		<Output clock="STREAM" name="read_1" type="PULL el=1 ael=8" width="1536">
-			<Stream name="Stream_48" sink="109" />
-		</Output>
-		<Output clock="STREAM" name="read_2" type="PULL el=1 ael=8" width="1536">
-			<Stream name="Stream_52" sink="113" />
-		</Output>
-		<Output clock="STREAM" name="read_3" type="PULL el=1 ael=8" width="1536">
-			<Stream name="Stream_56" sink="117" />
-		</Output>
-		<Output clock="MemoryControllerPro0_clk" name="Tag_Out" type="PUSH 1" width="1">
-			<Stream name="Stream_25" sink="23" />
-		</Output>
-		<Output clock="MemoryControllerPro0_clk" name="cmd_stream_maxj_a" type="PUSH 3" width="544">
-			<Stream name="Stream_33" sink="81" />
-		</Output>
-		<Output clock="MemoryControllerPro0_clk" name="cmd_stream_maxj_b" type="PUSH 3" width="544">
-			<Stream name="Stream_28" sink="77" />
-		</Output>
-		<Output clock="MemoryControllerPro0_clk" name="cmd_stream_maxj_c" type="PUSH 3" width="544">
-			<Stream name="Stream_38" sink="85" />
-		</Output>
-	</Node>
-	<Node id="23" instanceName="MemoryControllerPro0_IntSource" type="_A">
-		<Input clock="MemoryControllerPro0_clk" name="Tag_In" type="PUSH 1" width="1">
-			<Stream name="Stream_24" source="22" />
-		</Input>
-	</Node>
-	<Node id="113" instanceName="Stream_12" type="DualAspectMux">
-		<Input clock="STREAM" name="input" type="PULL el=1" width="1536">
-			<Stream name="Stream_114" source="22" />
-		</Input>
-		<Output clock="STREAM" name="output" type="PUSH 2" width="32">
-			<Stream name="Stream_115" sink="213" />
-		</Output>
-	</Node>
-	<Node id="117" instanceName="Stream_14" type="DualAspectMux">
-		<Input clock="STREAM" name="input" type="PULL el=1" width="1536">
-			<Stream name="Stream_118" source="22" />
-		</Input>
-		<Output clock="STREAM" name="output" type="PUSH 2" width="32">
-			<Stream name="Stream_119" sink="217" />
-		</Output>
-	</Node>
-	<Node id="85" instanceName="Stream_38_pipeline_4" type="Pipeline">
-		<Input clock="MemoryControllerPro0_clk" name="input" type="PUSH 3" width="544">
-			<Stream name="Stream_86" source="22" />
-		</Input>
-		<Output clock="MemoryControllerPro0_clk" name="output" type="PUSH 11" width="544">
-			<Stream name="Stream_87" sink="221" />
-		</Output>
-	</Node>
-	<Node id="81" instanceName="Stream_33_pipeline_4" type="Pipeline">
-		<Input clock="MemoryControllerPro0_clk" name="input" type="PUSH 3" width="544">
-			<Stream name="Stream_82" source="22" />
-		</Input>
-		<Output clock="MemoryControllerPro0_clk" name="output" type="PUSH 11" width="544">
-			<Stream name="Stream_83" sink="153" />
-		</Output>
-	</Node>
-	<Node id="213" instanceName="Stream_116" type="Fifo">
-		<Input clock="STREAM" name="input" type="PUSH 2" width="32">
-			<Stream name="Stream_214" source="113" />
-		</Input>
-		<Output clock="STREAM" name="output" type="PULL el=1 ael=2" width="32">
-			<Stream name="Stream_215" sink="0" />
-		</Output>
-	</Node>
-	<Node id="217" instanceName="Stream_120" type="Fifo">
-		<Input clock="STREAM" name="input" type="PUSH 2" width="32">
-			<Stream name="Stream_218" source="117" />
-		</Input>
-		<Output clock="STREAM" name="output" type="PULL el=1 ael=2" width="32">
-			<Stream name="Stream_219" sink="0" />
-		</Output>
-	</Node>
-	<Node id="221" instanceName="Stream_88" type="Fifo">
-		<Input clock="MemoryControllerPro0_clk" name="input" type="PUSH 11" width="544">
-			<Stream name="Stream_222" source="85" />
-		</Input>
-		<Output clock="DDR_CLK_c" name="output" type="PULL el=1" width="544">
-			<Stream name="Stream_223" sink="36" />
-		</Output>
-	</Node>
-	<Node id="0" instanceName="StreamFMAKernel" type="Kernel">
-		<PxgFile phase="original">StreamFMA-StreamFMAKernel-original.pxg</PxgFile>
-		<PxgFile phase="final-simulation">StreamFMA-StreamFMAKernel-final-simulation.pxg</PxgFile>
-		<Input clock="STREAM" name="inAT1" type="PULL el=1 ael=2" width="32">
-			<Stream name="Stream_200" source="197" />
-		</Input>
-		<Input clock="STREAM" name="inBT1" type="PULL el=1 ael=2" width="32">
-			<Stream name="Stream_204" source="201" />
-		</Input>
-		<Input clock="STREAM" name="inAT2" type="PULL el=1 ael=2" width="32">
-			<Stream name="Stream_208" source="205" />
-		</Input>
-		<Input clock="STREAM" name="inBT2" type="PULL el=1 ael=2" width="32">
-			<Stream name="Stream_212" source="209" />
-		</Input>
-		<Input clock="STREAM" name="inAT3" type="PULL el=1 ael=2" width="32">
-			<Stream name="Stream_216" source="213" />
-		</Input>
-		<Input clock="STREAM" name="inBT3" type="PULL el=1 ael=2" width="32">
-			<Stream name="Stream_220" source="217" />
-		</Input>
-		<Output clock="STREAM" name="oDataT1" type="PUSH 5" width="32">
-			<Stream name="Stream_16" sink="157" />
-		</Output>
-		<Output clock="STREAM" name="oDataT2" type="PUSH 5" width="32">
-			<Stream name="Stream_18" sink="145" />
-		</Output>
-		<Output clock="STREAM" name="oDataT3" type="PUSH 5" width="32">
-			<Stream name="Stream_21" sink="225" />
-		</Output>
-	</Node>
-	<Node id="36" instanceName="MemoryControllerInterface_c" type="Max5Mci">
-		<Input clock="DDR_CLK_c" name="cmd_stream_maxj" type="PULL el=1" width="544">
-			<Stream name="Stream_224" source="221" />
-		</Input>
-		<Output clock="DDR_CLK_c" name="read_stream_maxj" type="PUSH 1" width="512">
-			<Stream name="Stream_39" sink="73" />
-		</Output>
-	</Node>
-	<Node id="225" instanceName="Stream_122" type="Fifo">
-		<Input clock="STREAM" name="input" type="PUSH 5" width="32">
-			<Stream name="Stream_226" source="0" />
-		</Input>
-		<Output clock="PCIE" name="output" type="PULL el=1" width="32">
-			<Stream name="Stream_227" sink="121" />
-		</Output>
-	</Node>
-	<Node id="145" instanceName="Stream_94" type="Fifo">
-		<Input clock="STREAM" name="input" type="PUSH 5" width="32">
-			<Stream name="Stream_146" source="0" />
-		</Input>
-		<Output clock="STREAM" name="output" type="PULL el=1" width="32">
-			<Stream name="Stream_147" sink="93" />
-		</Output>
-	</Node>
-	<Node id="121" instanceName="Stream_20" type="DualAspectReg">
-		<Input clock="PCIE" name="input" type="PULL el=1" width="32">
-			<Stream name="Stream_228" source="225" />
-		</Input>
-		<Output clock="PCIE" name="output" type="PULL el=1" width="128">
-			<Stream name="Stream_123" sink="133" />
-		</Output>
-	</Node>
-	<Node id="93" instanceName="Stream_64" type="DualAspectReg">
-		<Input clock="STREAM" name="input" type="PULL el=1" width="32">
-			<Stream name="Stream_148" source="145" />
-		</Input>
-		<Output clock="STREAM" name="output" type="PULL el=1" width="1536">
-			<Stream name="Stream_95" sink="129" />
-		</Output>
-	</Node>
-</ManagerGraph>

tests/StreamFMA_MAX5C_DFE_SIM/scratch/Manager_StreamFMA_Original.mxg

@@ -1,214 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" ?>
-<ManagerGraph version="2018.3.1" design_name="Manager_StreamFMA" compilation_phase="Original" hardwareBuild="false">
-	<Node id="45" instanceName="addrgen_cmd_MemoryControllerPro0_inBT2" type="McpAddressGenerator">
-		<Output clock="STREAM" name="cgen_out_0" type="PUSH 1" width="64">
-			<Stream name="Stream_47" sink="22" />
-		</Output>
-	</Node>
-	<Node id="61" instanceName="addrgen_cmd_MemoryControllerPro0_oDataT2" type="McpAddressGenerator">
-		<Output clock="STREAM" name="cgen_out_0" type="PUSH 1" width="64">
-			<Stream name="Stream_63" sink="22" />
-		</Output>
-	</Node>
-	<Node id="5" instanceName="inBT1" type="Input">
-		<Output clock="PCIE" name="inBT1" type="PUSH 2" width="128">
-			<Stream name="Stream_6" sink="0" />
-		</Output>
-	</Node>
-	<Node id="49" instanceName="addrgen_cmd_MemoryControllerPro0_inAT3" type="McpAddressGenerator">
-		<Output clock="STREAM" name="cgen_out_0" type="PUSH 1" width="64">
-			<Stream name="Stream_51" sink="22" />
-		</Output>
-	</Node>
-	<Node id="2" instanceName="inAT1" type="Input">
-		<Output clock="PCIE" name="inAT1" type="PUSH 2" width="128">
-			<Stream name="Stream_3" sink="0" />
-		</Output>
-	</Node>
-	<Node id="53" instanceName="addrgen_cmd_MemoryControllerPro0_inBT3" type="McpAddressGenerator">
-		<Output clock="STREAM" name="cgen_out_0" type="PUSH 1" width="64">
-			<Stream name="Stream_55" sink="22" />
-		</Output>
-	</Node>
-	<Node id="57" instanceName="addrgen_cmd_MemoryControllerPro0_oDataT1" type="McpAddressGenerator">
-		<Output clock="STREAM" name="cgen_out_0" type="PUSH 1" width="64">
-			<Stream name="Stream_59" sink="22" />
-		</Output>
-	</Node>
-	<Node id="41" instanceName="addrgen_cmd_MemoryControllerPro0_inAT2" type="McpAddressGenerator">
-		<Output clock="STREAM" name="cgen_out_0" type="PUSH 1" width="64">
-			<Stream name="Stream_43" sink="22" />
-		</Output>
-	</Node>
-	<Node id="65" instanceName="Stream_34_pipeline_4" type="Pipeline">
-		<Input clock="DDR_CLK_a" name="input" type="PUSH 1" width="-1">
-			<Stream name="Stream_66" source="31" />
-		</Input>
-		<Output clock="DDR_CLK_a" name="output" type="PUSH 9" width="-1">
-			<Stream name="Stream_67" sink="22" />
-		</Output>
-	</Node>
-	<Node id="77" instanceName="Stream_28_pipeline_4" type="Pipeline">
-		<Input clock="MemoryControllerPro0_clk" name="input" type="PUSH 3" width="-1">
-			<Stream name="Stream_78" source="22" />
-		</Input>
-		<Output clock="MemoryControllerPro0_clk" name="output" type="PUSH 11" width="-1">
-			<Stream name="Stream_79" sink="26" />
-		</Output>
-	</Node>
-	<Node id="26" instanceName="MemoryControllerInterface_b" type="Max5Mci">
-		<Input clock="DDR_CLK_b" name="cmd_stream_maxj" type="PULL el=1" width="544">
-			<Stream name="Stream_80" source="77" />
-		</Input>
-		<Output clock="DDR_CLK_b" name="read_stream_maxj" type="PUSH 1" width="512">
-			<Stream name="Stream_29" sink="69" />
-		</Output>
-	</Node>
-	<Node id="69" instanceName="Stream_29_pipeline_4" type="Pipeline">
-		<Input clock="DDR_CLK_b" name="input" type="PUSH 1" width="-1">
-			<Stream name="Stream_70" source="26" />
-		</Input>
-		<Output clock="DDR_CLK_b" name="output" type="PUSH 9" width="-1">
-			<Stream name="Stream_71" sink="22" />
-		</Output>
-	</Node>
-	<Node id="31" instanceName="MemoryControllerInterface_a" type="Max5Mci">
-		<Input clock="DDR_CLK_a" name="cmd_stream_maxj" type="PULL el=1" width="544">
-			<Stream name="Stream_84" source="81" />
-		</Input>
-		<Output clock="DDR_CLK_a" name="read_stream_maxj" type="PUSH 1" width="512">
-			<Stream name="Stream_34" sink="65" />
-		</Output>
-	</Node>
-	<Node id="81" instanceName="Stream_33_pipeline_4" type="Pipeline">
-		<Input clock="MemoryControllerPro0_clk" name="input" type="PUSH 3" width="-1">
-			<Stream name="Stream_82" source="22" />
-		</Input>
-		<Output clock="MemoryControllerPro0_clk" name="output" type="PUSH 11" width="-1">
-			<Stream name="Stream_83" sink="31" />
-		</Output>
-	</Node>
-	<Node id="22" instanceName="MemoryControllerPro0" type="MemoryControllerPro">
-		<Input clock="MemoryControllerPro0_clk" name="read_stream_maxj_a" type="PULL el=1 ael=3" width="512">
-			<Stream name="Stream_68" source="65" />
-		</Input>
-		<Input clock="MemoryControllerPro0_clk" name="read_stream_maxj_b" type="PULL el=1 ael=3" width="512">
-			<Stream name="Stream_72" source="69" />
-		</Input>
-		<Input clock="MemoryControllerPro0_clk" name="read_stream_maxj_c" type="PULL el=1 ael=3" width="512">
-			<Stream name="Stream_76" source="73" />
-		</Input>
-		<Input clock="MemoryControllerPro0_clk" name="read_command_0" type="PUSH 8" width="64">
-			<Stream name="Stream_42" source="41" />
-		</Input>
-		<Input clock="MemoryControllerPro0_clk" name="read_command_1" type="PUSH 8" width="64">
-			<Stream name="Stream_46" source="45" />
-		</Input>
-		<Input clock="MemoryControllerPro0_clk" name="read_command_2" type="PUSH 8" width="64">
-			<Stream name="Stream_50" source="49" />
-		</Input>
-		<Input clock="MemoryControllerPro0_clk" name="read_command_3" type="PUSH 8" width="64">
-			<Stream name="Stream_54" source="53" />
-		</Input>
-		<Input clock="STREAM" name="write_0" type="PUSH 8" width="1536">
-			<Stream name="Stream_60" source="0" />
-		</Input>
-		<Input clock="STREAM" name="write_1" type="PUSH 8" width="1536">
-			<Stream name="Stream_64" source="0" />
-		</Input>
-		<Input clock="MemoryControllerPro0_clk" name="write_command_0" type="PUSH 8" width="64">
-			<Stream name="Stream_58" source="57" />
-		</Input>
-		<Input clock="MemoryControllerPro0_clk" name="write_command_1" type="PUSH 8" width="64">
-			<Stream name="Stream_62" source="61" />
-		</Input>
-		<Output clock="STREAM" name="read_0" type="PULL el=1 ael=8" width="1536">
-			<Stream name="Stream_44" sink="0" />
-		</Output>
-		<Output clock="STREAM" name="read_1" type="PULL el=1 ael=8" width="1536">
-			<Stream name="Stream_48" sink="0" />
-		</Output>
-		<Output clock="STREAM" name="read_2" type="PULL el=1 ael=8" width="1536">
-			<Stream name="Stream_52" sink="0" />
-		</Output>
-		<Output clock="STREAM" name="read_3" type="PULL el=1 ael=8" width="1536">
-			<Stream name="Stream_56" sink="0" />
-		</Output>
-		<Output clock="MemoryControllerPro0_clk" name="Tag_Out" type="PUSH 1" width="1">
-			<Stream name="Stream_25" sink="23" />
-		</Output>
-		<Output clock="MemoryControllerPro0_clk" name="cmd_stream_maxj_a" type="PUSH 3" width="544">
-			<Stream name="Stream_33" sink="81" />
-		</Output>
-		<Output clock="MemoryControllerPro0_clk" name="cmd_stream_maxj_b" type="PUSH 3" width="544">
-			<Stream name="Stream_28" sink="77" />
-		</Output>
-		<Output clock="MemoryControllerPro0_clk" name="cmd_stream_maxj_c" type="PUSH 3" width="544">
-			<Stream name="Stream_38" sink="85" />
-		</Output>
-	</Node>
-	<Node id="0" instanceName="StreamFMAKernel" type="Kernel">
-		<PxgFile phase="original">StreamFMA-StreamFMAKernel-original.pxg</PxgFile>
-		<Input clock="STREAM" name="inAT1" type="PULL el=1 ael=2" width="32">
-			<Stream name="Stream_1" source="2" />
-		</Input>
-		<Input clock="STREAM" name="inBT1" type="PULL el=1 ael=2" width="32">
-			<Stream name="Stream_4" source="5" />
-		</Input>
-		<Input clock="STREAM" name="inAT2" type="PULL el=1 ael=2" width="32">
-			<Stream name="Stream_8" source="22" />
-		</Input>
-		<Input clock="STREAM" name="inBT2" type="PULL el=1 ael=2" width="32">
-			<Stream name="Stream_10" source="22" />
-		</Input>
-		<Input clock="STREAM" name="inAT3" type="PULL el=1 ael=2" width="32">
-			<Stream name="Stream_12" source="22" />
-		</Input>
-		<Input clock="STREAM" name="inBT3" type="PULL el=1 ael=2" width="32">
-			<Stream name="Stream_14" source="22" />
-		</Input>
-		<Output clock="STREAM" name="oDataT1" type="PUSH 5" width="32">
-			<Stream name="Stream_16" sink="22" />
-		</Output>
-		<Output clock="STREAM" name="oDataT2" type="PUSH 5" width="32">
-			<Stream name="Stream_18" sink="22" />
-		</Output>
-		<Output clock="STREAM" name="oDataT3" type="PUSH 5" width="32">
-			<Stream name="Stream_21" sink="19" />
-		</Output>
-	</Node>
-	<Node id="23" instanceName="MemoryControllerPro0_IntSource" type="_A">
-		<Input clock="clk" name="Tag_In" type="PUSH 1" width="1">
-			<Stream name="Stream_24" source="22" />
-		</Input>
-	</Node>
-	<Node id="85" instanceName="Stream_38_pipeline_4" type="Pipeline">
-		<Input clock="MemoryControllerPro0_clk" name="input" type="PUSH 3" width="-1">
-			<Stream name="Stream_86" source="22" />
-		</Input>
-		<Output clock="MemoryControllerPro0_clk" name="output" type="PUSH 11" width="-1">
-			<Stream name="Stream_87" sink="36" />
-		</Output>
-	</Node>
-	<Node id="19" instanceName="oDataT3" type="Output">
-		<Input clock="PCIE" name="oDataT3" type="PUSH 1" width="128">
-			<Stream name="Stream_20" source="0" />
-		</Input>
-	</Node>
-	<Node id="36" instanceName="MemoryControllerInterface_c" type="Max5Mci">
-		<Input clock="DDR_CLK_c" name="cmd_stream_maxj" type="PULL el=1" width="544">
-			<Stream name="Stream_88" source="85" />
-		</Input>
-		<Output clock="DDR_CLK_c" name="read_stream_maxj" type="PUSH 1" width="512">
-			<Stream name="Stream_39" sink="73" />
-		</Output>
-	</Node>
-	<Node id="73" instanceName="Stream_39_pipeline_4" type="Pipeline">
-		<Input clock="DDR_CLK_c" name="input" type="PUSH 1" width="-1">
-			<Stream name="Stream_74" source="36" />
-		</Input>
-		<Output clock="DDR_CLK_c" name="output" type="PUSH 9" width="-1">
-			<Stream name="Stream_75" sink="22" />
-		</Output>
-	</Node>
-</ManagerGraph>

tests/StreamFMA_MAX5C_DFE_SIM/scratch/StreamFMA-StreamFMAKernel-final-simulation.pxg

@@ -1,485 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" ?>
-<Graph version="2018.3.1" pxg_version="2" maxfile_name="StreamFMA" design_name="StreamFMAKernel" compilation_phase="final-simulation" frequency="100,00">
-	<Node criticalPaths="[]" group="[]" id="22" isControl="true" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeInputMappedReg">
-		<Output latency="0" name="io_oDataT1_force_disabled" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>Scalar input (io_oDataT1_force_disabled)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:31)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>io_oDataT1_force_disabled</Name>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="23" dst_node_input="a" src_node_id="22" src_node_output="io_oDataT1_force_disabled" />
-	<Node criticalPaths="[]" group="[]" id="23" isControl="true" isVisible="false" pipelineFactor="0.0" powerUsage="N/A" type="NodeNot">
-		<Input name="a" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Output latency="0" name="result" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>~</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:31)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="25" dst_node_input="output_control" src_node_id="23" src_node_output="result" />
-	<Node criticalPaths="[]" group="[]" id="0" isControl="true" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeInputMappedReg">
-		<Output latency="0" name="io_inAT1_force_disabled" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>Scalar input (io_inAT1_force_disabled)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:15)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>io_inAT1_force_disabled</Name>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="1" dst_node_input="a" src_node_id="0" src_node_output="io_inAT1_force_disabled" />
-	<Node criticalPaths="[]" group="[]" id="1" isControl="true" isVisible="false" pipelineFactor="0.0" powerUsage="N/A" type="NodeNot">
-		<Input name="a" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Output latency="0" name="result" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>~</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:15)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="2" dst_node_input="enable" src_node_id="1" src_node_output="result" />
-	<Node criticalPaths="[0]" group="[]" id="2" isControl="false" isVisible="true" pipelineFactor="1.0" powerUsage="N/A" type="NodeInput">
-		<Input name="enable" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Output latency="5" name="data" type="dfeOffsetFix(32, 0, TWOSCOMPLEMENT)" />
-		<Text>Input(inAT1)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:15)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>inAT1</Name>
-	</Node>
-	<Edge criticalPaths="[0]" dst_node_id="18" dst_node_input="a" src_node_id="2" src_node_output="data" />
-	<Node criticalPaths="[]" group="[]" id="3" isControl="true" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeInputMappedReg">
-		<Output latency="0" name="io_inBT1_force_disabled" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>Scalar input (io_inBT1_force_disabled)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:16)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>io_inBT1_force_disabled</Name>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="4" dst_node_input="a" src_node_id="3" src_node_output="io_inBT1_force_disabled" />
-	<Node criticalPaths="[]" group="[]" id="4" isControl="true" isVisible="false" pipelineFactor="0.0" powerUsage="N/A" type="NodeNot">
-		<Input name="a" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Output latency="0" name="result" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>~</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:16)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="5" dst_node_input="enable" src_node_id="4" src_node_output="result" />
-	<Node criticalPaths="[1]" group="[]" id="5" isControl="false" isVisible="true" pipelineFactor="1.0" powerUsage="N/A" type="NodeInput">
-		<Input name="enable" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Output latency="5" name="data" type="dfeOffsetFix(32, 0, TWOSCOMPLEMENT)" />
-		<Text>Input(inBT1)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:16)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>inBT1</Name>
-	</Node>
-	<Edge criticalPaths="[1]" dst_node_id="18" dst_node_input="b" src_node_id="5" src_node_output="data" />
-	<Node criticalPaths="[0, 1]" group="[]" id="18" isControl="false" isVisible="true" pipelineFactor="1.0" powerUsage="N/A" type="NodeAdd">
-		<Input name="a" type="dfeOffsetFix(32, 0, TWOSCOMPLEMENT)" />
-		<Input name="b" type="dfeOffsetFix(32, 0, TWOSCOMPLEMENT)" />
-		<Output latency="1" name="result" type="dfeOffsetFix(32, 0, TWOSCOMPLEMENT)" />
-		<Text>+</Text>
-		<ResourceUsage DSPs="0" FFs="32" FMems="0" LUTs="64" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.types.base.DFEVar.add(DFEVar.java:1010)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:27)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-	</Node>
-	<Edge criticalPaths="[0, 1]" dst_node_id="25" dst_node_input="data" src_node_id="18" src_node_output="result" />
-	<Node criticalPaths="[0, 1]" group="[]" id="25" isControl="false" isVisible="true" pipelineFactor="1.0" powerUsage="N/A" type="NodeOutput">
-		<Input name="output_control" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Input name="data" type="dfeOffsetFix(32, 0, TWOSCOMPLEMENT)" />
-		<Text>Output(oDataT1)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:31)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>oDataT1</Name>
-	</Node>
-	<Node criticalPaths="[]" group="[]" id="27" isControl="true" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeInputMappedReg">
-		<Output latency="0" name="io_oDataT2_force_disabled" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>Scalar input (io_oDataT2_force_disabled)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:32)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>io_oDataT2_force_disabled</Name>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="28" dst_node_input="a" src_node_id="27" src_node_output="io_oDataT2_force_disabled" />
-	<Node criticalPaths="[]" group="[]" id="28" isControl="true" isVisible="false" pipelineFactor="0.0" powerUsage="N/A" type="NodeNot">
-		<Input name="a" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Output latency="0" name="result" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>~</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:32)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="30" dst_node_input="output_control" src_node_id="28" src_node_output="result" />
-	<Node criticalPaths="[]" group="[]" id="6" isControl="true" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeInputMappedReg">
-		<Output latency="0" name="io_inAT2_force_disabled" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>Scalar input (io_inAT2_force_disabled)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:19)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>io_inAT2_force_disabled</Name>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="7" dst_node_input="a" src_node_id="6" src_node_output="io_inAT2_force_disabled" />
-	<Node criticalPaths="[]" group="[]" id="7" isControl="true" isVisible="false" pipelineFactor="0.0" powerUsage="N/A" type="NodeNot">
-		<Input name="a" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Output latency="0" name="result" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>~</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:19)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="8" dst_node_input="enable" src_node_id="7" src_node_output="result" />
-	<Node criticalPaths="[2]" group="[]" id="8" isControl="false" isVisible="true" pipelineFactor="1.0" powerUsage="N/A" type="NodeInput">
-		<Input name="enable" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Output latency="5" name="data" type="dfeOffsetFix(32, 0, TWOSCOMPLEMENT)" />
-		<Text>Input(inAT2)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:19)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>inAT2</Name>
-	</Node>
-	<Edge criticalPaths="[2]" dst_node_id="19" dst_node_input="a" src_node_id="8" src_node_output="data" />
-	<Node criticalPaths="[]" group="[]" id="9" isControl="true" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeInputMappedReg">
-		<Output latency="0" name="io_inBT2_force_disabled" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>Scalar input (io_inBT2_force_disabled)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:20)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>io_inBT2_force_disabled</Name>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="10" dst_node_input="a" src_node_id="9" src_node_output="io_inBT2_force_disabled" />
-	<Node criticalPaths="[]" group="[]" id="10" isControl="true" isVisible="false" pipelineFactor="0.0" powerUsage="N/A" type="NodeNot">
-		<Input name="a" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Output latency="0" name="result" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>~</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:20)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="11" dst_node_input="enable" src_node_id="10" src_node_output="result" />
-	<Node criticalPaths="[3]" group="[]" id="11" isControl="false" isVisible="true" pipelineFactor="1.0" powerUsage="N/A" type="NodeInput">
-		<Input name="enable" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Output latency="5" name="data" type="dfeOffsetFix(32, 0, TWOSCOMPLEMENT)" />
-		<Text>Input(inBT2)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:20)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>inBT2</Name>
-	</Node>
-	<Edge criticalPaths="[3]" dst_node_id="19" dst_node_input="b" src_node_id="11" src_node_output="data" />
-	<Node criticalPaths="[2, 3]" group="[]" id="19" isControl="false" isVisible="true" pipelineFactor="1.0" powerUsage="N/A" type="NodeMul">
-		<Input name="a" type="dfeOffsetFix(32, 0, TWOSCOMPLEMENT)" />
-		<Input name="b" type="dfeOffsetFix(32, 0, TWOSCOMPLEMENT)" />
-		<Output latency="6" name="result" type="dfeOffsetFix(32, 0, TWOSCOMPLEMENT)" />
-		<Text>*</Text>
-		<ResourceUsage DSPs="0" FFs="192" FMems="0" LUTs="224" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.types.base.DFEVar.mul(DFEVar.java:1118)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:28)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-	</Node>
-	<Edge criticalPaths="[2, 3]" dst_node_id="30" dst_node_input="data" src_node_id="19" src_node_output="result" />
-	<Node criticalPaths="[2, 3]" group="[]" id="30" isControl="false" isVisible="true" pipelineFactor="1.0" powerUsage="N/A" type="NodeOutput">
-		<Input name="output_control" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Input name="data" type="dfeOffsetFix(32, 0, TWOSCOMPLEMENT)" />
-		<Text>Output(oDataT2)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:32)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>oDataT2</Name>
-	</Node>
-	<Node criticalPaths="[]" group="[]" id="32" isControl="true" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeInputMappedReg">
-		<Output latency="0" name="io_oDataT3_force_disabled" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>Scalar input (io_oDataT3_force_disabled)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:33)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>io_oDataT3_force_disabled</Name>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="33" dst_node_input="a" src_node_id="32" src_node_output="io_oDataT3_force_disabled" />
-	<Node criticalPaths="[]" group="[]" id="33" isControl="true" isVisible="false" pipelineFactor="0.0" powerUsage="N/A" type="NodeNot">
-		<Input name="a" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Output latency="0" name="result" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>~</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:33)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="35" dst_node_input="output_control" src_node_id="33" src_node_output="result" />
-	<Node criticalPaths="[]" group="[]" id="12" isControl="true" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeInputMappedReg">
-		<Output latency="0" name="io_inAT3_force_disabled" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>Scalar input (io_inAT3_force_disabled)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:23)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>io_inAT3_force_disabled</Name>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="13" dst_node_input="a" src_node_id="12" src_node_output="io_inAT3_force_disabled" />
-	<Node criticalPaths="[]" group="[]" id="13" isControl="true" isVisible="false" pipelineFactor="0.0" powerUsage="N/A" type="NodeNot">
-		<Input name="a" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Output latency="0" name="result" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>~</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:23)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="14" dst_node_input="enable" src_node_id="13" src_node_output="result" />
-	<Node criticalPaths="[4]" group="[]" id="14" isControl="false" isVisible="true" pipelineFactor="1.0" powerUsage="N/A" type="NodeInput">
-		<Input name="enable" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Output latency="5" name="data" type="dfeOffsetFix(32, 0, TWOSCOMPLEMENT)" />
-		<Text>Input(inAT3)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:23)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>inAT3</Name>
-	</Node>
-	<Edge criticalPaths="[4]" dst_node_id="20" dst_node_input="a" src_node_id="14" src_node_output="data" />
-	<Node criticalPaths="[]" group="[]" id="15" isControl="true" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeInputMappedReg">
-		<Output latency="0" name="io_inBT3_force_disabled" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>Scalar input (io_inBT3_force_disabled)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:24)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>io_inBT3_force_disabled</Name>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="16" dst_node_input="a" src_node_id="15" src_node_output="io_inBT3_force_disabled" />
-	<Node criticalPaths="[]" group="[]" id="16" isControl="true" isVisible="false" pipelineFactor="0.0" powerUsage="N/A" type="NodeNot">
-		<Input name="a" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Output latency="0" name="result" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>~</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:24)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="17" dst_node_input="enable" src_node_id="16" src_node_output="result" />
-	<Node criticalPaths="[5]" group="[]" id="17" isControl="false" isVisible="true" pipelineFactor="1.0" powerUsage="N/A" type="NodeInput">
-		<Input name="enable" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Output latency="5" name="data" type="dfeOffsetFix(32, 0, TWOSCOMPLEMENT)" />
-		<Text>Input(inBT3)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:24)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>inBT3</Name>
-	</Node>
-	<Edge criticalPaths="[5]" dst_node_id="20" dst_node_input="b" src_node_id="17" src_node_output="data" />
-	<Node criticalPaths="[4, 5]" group="[]" id="20" isControl="false" isVisible="true" pipelineFactor="1.0" powerUsage="N/A" type="NodeAdd">
-		<Input name="a" type="dfeOffsetFix(32, 0, TWOSCOMPLEMENT)" />
-		<Input name="b" type="dfeOffsetFix(32, 0, TWOSCOMPLEMENT)" />
-		<Output latency="1" name="result" type="dfeOffsetFix(32, 0, TWOSCOMPLEMENT)" />
-		<Text>+</Text>
-		<ResourceUsage DSPs="0" FFs="32" FMems="0" LUTs="64" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.types.base.DFEVar.add(DFEVar.java:1010)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:29)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-	</Node>
-	<Edge criticalPaths="[4, 5]" dst_node_id="35" dst_node_input="data" src_node_id="20" src_node_output="result" />
-	<Node criticalPaths="[4, 5]" group="[]" id="35" isControl="false" isVisible="true" pipelineFactor="1.0" powerUsage="N/A" type="NodeOutput">
-		<Input name="output_control" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Input name="data" type="dfeOffsetFix(32, 0, TWOSCOMPLEMENT)" />
-		<Text>Output(oDataT3)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:33)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>oDataT3</Name>
-	</Node>
-	<Node criticalPaths="[]" group="[]" id="40" isControl="false" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeConstantRawBits">
-		<Output latency="0" name="value" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>{HWOffsetFix:1, 0, UNSIGNED}\n0x1; 1.0</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Value>1</Value>
-		<HexValue>0x1</HexValue>
-		<NumericValue>1.0</NumericValue>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="41" dst_node_input="load" src_node_id="40" src_node_output="value" />
-	<Node criticalPaths="[]" group="[]" id="50" isControl="false" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeConstantRawBits">
-		<Output latency="0" name="value" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>{HWOffsetFix:1, 0, UNSIGNED}\n0x1; 1.0</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Value>1</Value>
-		<HexValue>0x1</HexValue>
-		<NumericValue>1.0</NumericValue>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="38" dst_node_input="enable" src_node_id="50" src_node_output="value" />
-	<Node criticalPaths="[]" group="[]" id="37" isControl="false" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeConstantRawBits">
-		<Output latency="0" name="value" type="dfeOffsetFix(49, 0, UNSIGNED)" />
-		<Text>{HWOffsetFix:49, 0, UNSIGNED}\n0x1000000000000; 2.81474976710656E14</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Value>1000000000000000000000000000000000000000000000000</Value>
-		<HexValue>0x1000000000000</HexValue>
-		<NumericValue>2.81474976710656E14</NumericValue>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="38" dst_node_input="max" src_node_id="37" src_node_output="value" />
-	<Node criticalPaths="[]" group="[]" id="38" isControl="false" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeCounter">
-		<Input name="enable" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Input name="max" type="dfeOffsetFix(49, 0, UNSIGNED)" />
-		<Output latency="0" name="count" type="dfeOffsetFix(48, 0, UNSIGNED)" />
-		<Output latency="0" name="wrap" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>Counter(NUMERIC_INCREMENTING)\nInc: 1\nReset: 0\nInit: 0</Text>
-		<ResourceUsage DSPs="0" FFs="48" FMems="0" LUTs="48" />
-		<OriginStackTrace>com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Increment>1</Increment>
-		<WrapValue>0</WrapValue>
-		<InitValue>0</InitValue>
-		<CountMode>NUMERIC_INCREMENTING</CountMode>
-		<WrapMode>COUNT_LT_MAX_THEN_WRAP</WrapMode>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="39" dst_node_input="input" src_node_id="38" src_node_output="count" />
-	<Node criticalPaths="[]" group="[]" id="39" isControl="false" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeStreamOffset">
-		<Input name="input" type="dfeOffsetFix(48, 0, UNSIGNED)" />
-		<Output latency="1" name="output" type="dfeOffsetFix(48, 0, UNSIGNED)" />
-		<Text>stream offset: 1</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="41" dst_node_input="data" src_node_id="39" src_node_output="output" />
-	<Node criticalPaths="[]" group="[]" id="41" isControl="false" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeOutputMappedReg">
-		<Input name="load" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Input name="data" type="dfeOffsetFix(48, 0, UNSIGNED)" />
-		<Text>Scalar output (current_run_cycle_count)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>current_run_cycle_count</Name>
-	</Node>
-	<Node criticalPaths="[]" group="[]" id="49" isControl="false" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeConstantRawBits">
-		<Output latency="0" name="value" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>{HWOffsetFix:1, 0, UNSIGNED}\n0x1; 1.0</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Value>1</Value>
-		<HexValue>0x1</HexValue>
-		<NumericValue>1.0</NumericValue>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="44" dst_node_input="enable" src_node_id="49" src_node_output="value" />
-	<Node criticalPaths="[]" group="[]" id="43" isControl="false" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeConstantRawBits">
-		<Output latency="0" name="value" type="dfeOffsetFix(49, 0, UNSIGNED)" />
-		<Text>{HWOffsetFix:49, 0, UNSIGNED}\n0x1000000000000; 2.81474976710656E14</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Value>1000000000000000000000000000000000000000000000000</Value>
-		<HexValue>0x1000000000000</HexValue>
-		<NumericValue>2.81474976710656E14</NumericValue>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="44" dst_node_input="max" src_node_id="43" src_node_output="value" />
-	<Node criticalPaths="[]" group="[]" id="44" isControl="false" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeCounter">
-		<Input name="enable" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Input name="max" type="dfeOffsetFix(49, 0, UNSIGNED)" />
-		<Output latency="0" name="count" type="dfeOffsetFix(48, 0, UNSIGNED)" />
-		<Output latency="0" name="wrap" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>Counter(NUMERIC_INCREMENTING)\nInc: 1\nReset: 0\nInit: 0</Text>
-		<ResourceUsage DSPs="0" FFs="48" FMems="0" LUTs="48" />
-		<OriginStackTrace>com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Increment>1</Increment>
-		<WrapValue>0</WrapValue>
-		<InitValue>0</InitValue>
-		<CountMode>NUMERIC_INCREMENTING</CountMode>
-		<WrapMode>COUNT_LT_MAX_THEN_WRAP</WrapMode>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="48" dst_node_input="a" src_node_id="44" src_node_output="count" />
-	<Node criticalPaths="[]" group="[]" id="46" isControl="true" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeInputMappedReg">
-		<Output latency="0" name="run_cycle_count" type="dfeOffsetFix(48, 0, UNSIGNED)" />
-		<Text>Scalar input (run_cycle_count)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>run_cycle_count</Name>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="48" dst_node_input="b" src_node_id="46" src_node_output="run_cycle_count" />
-	<Node criticalPaths="[]" group="[]" id="48" isControl="false" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeEqInlined">
-		<Input name="a" type="dfeOffsetFix(48, 0, UNSIGNED)" />
-		<Input name="b" type="dfeOffsetFix(48, 0, UNSIGNED)" />
-		<Output latency="1" name="result" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>==</Text>
-		<ResourceUsage DSPs="0" FFs="1" FMems="0" LUTs="2" />
-		<OriginStackTrace>com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="45" dst_node_input="start" src_node_id="48" src_node_output="result" />
-	<Node criticalPaths="[]" group="[]" id="45" isControl="false" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeFlush">
-		<Input name="start" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>flush on trigger</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-	</Node>
-</Graph>

tests/StreamFMA_MAX5C_DFE_SIM/scratch/StreamFMA-StreamFMAKernel-original.pxg

@@ -1,556 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" ?>
-<Graph version="2018.3.1" pxg_version="2" maxfile_name="StreamFMA" design_name="StreamFMAKernel" compilation_phase="original" frequency="0,00">
-	<Node criticalPaths="[]" group="[]" id="21" isControl="false" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeConstantRawBits">
-		<Output latency="0" name="value" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>{HWOffsetFix:1, 0, UNSIGNED}\n0x1; 1.0</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:31)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Value>1</Value>
-		<HexValue>0x1</HexValue>
-		<NumericValue>1.0</NumericValue>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="24" dst_node_input="a" src_node_id="21" src_node_output="value" />
-	<Node criticalPaths="[]" group="[]" id="22" isControl="true" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeInputMappedReg">
-		<Output latency="0" name="io_oDataT1_force_disabled" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>Scalar input (io_oDataT1_force_disabled)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:31)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>io_oDataT1_force_disabled</Name>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="23" dst_node_input="a" src_node_id="22" src_node_output="io_oDataT1_force_disabled" />
-	<Node criticalPaths="[]" group="[]" id="23" isControl="true" isVisible="false" pipelineFactor="0.0" powerUsage="N/A" type="NodeNot">
-		<Input name="a" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Output latency="0" name="result" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>~</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:31)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="24" dst_node_input="b" src_node_id="23" src_node_output="result" />
-	<Node criticalPaths="[]" group="[]" id="24" isControl="false" isVisible="false" pipelineFactor="0.0" powerUsage="N/A" type="NodeAnd">
-		<Input name="a" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Input name="b" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Output latency="0" name="result" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>&amp;</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="1" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:31)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="25" dst_node_input="output_control" src_node_id="24" src_node_output="result" />
-	<Node criticalPaths="[]" group="[]" id="0" isControl="true" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeInputMappedReg">
-		<Output latency="0" name="io_inAT1_force_disabled" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>Scalar input (io_inAT1_force_disabled)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:15)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>io_inAT1_force_disabled</Name>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="1" dst_node_input="a" src_node_id="0" src_node_output="io_inAT1_force_disabled" />
-	<Node criticalPaths="[]" group="[]" id="1" isControl="true" isVisible="false" pipelineFactor="0.0" powerUsage="N/A" type="NodeNot">
-		<Input name="a" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Output latency="0" name="result" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>~</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:15)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="2" dst_node_input="enable" src_node_id="1" src_node_output="result" />
-	<Node criticalPaths="[]" group="[]" id="2" isControl="false" isVisible="true" pipelineFactor="1.0" powerUsage="N/A" type="NodeInput">
-		<Input name="enable" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Output latency="5" name="data" type="dfeOffsetFix(32, 0, TWOSCOMPLEMENT)" />
-		<Text>Input(inAT1)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:15)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>inAT1</Name>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="18" dst_node_input="a" src_node_id="2" src_node_output="data" />
-	<Node criticalPaths="[]" group="[]" id="3" isControl="true" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeInputMappedReg">
-		<Output latency="0" name="io_inBT1_force_disabled" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>Scalar input (io_inBT1_force_disabled)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:16)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>io_inBT1_force_disabled</Name>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="4" dst_node_input="a" src_node_id="3" src_node_output="io_inBT1_force_disabled" />
-	<Node criticalPaths="[]" group="[]" id="4" isControl="true" isVisible="false" pipelineFactor="0.0" powerUsage="N/A" type="NodeNot">
-		<Input name="a" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Output latency="0" name="result" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>~</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:16)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="5" dst_node_input="enable" src_node_id="4" src_node_output="result" />
-	<Node criticalPaths="[]" group="[]" id="5" isControl="false" isVisible="true" pipelineFactor="1.0" powerUsage="N/A" type="NodeInput">
-		<Input name="enable" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Output latency="5" name="data" type="dfeOffsetFix(32, 0, TWOSCOMPLEMENT)" />
-		<Text>Input(inBT1)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:16)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>inBT1</Name>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="18" dst_node_input="b" src_node_id="5" src_node_output="data" />
-	<Node criticalPaths="[]" group="[]" id="18" isControl="false" isVisible="true" pipelineFactor="1.0" powerUsage="N/A" type="NodeAdd">
-		<Input name="a" type="dfeOffsetFix(32, 0, TWOSCOMPLEMENT)" />
-		<Input name="b" type="dfeOffsetFix(32, 0, TWOSCOMPLEMENT)" />
-		<Output latency="1" name="result" type="dfeOffsetFix(32, 0, TWOSCOMPLEMENT)" />
-		<Text>+</Text>
-		<ResourceUsage DSPs="0" FFs="32" FMems="0" LUTs="64" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.types.base.DFEVar.add(DFEVar.java:1010)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:27)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="25" dst_node_input="data" src_node_id="18" src_node_output="result" />
-	<Node criticalPaths="[]" group="[]" id="25" isControl="false" isVisible="true" pipelineFactor="1.0" powerUsage="N/A" type="NodeOutput">
-		<Input name="output_control" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Input name="data" type="dfeOffsetFix(32, 0, TWOSCOMPLEMENT)" />
-		<Text>Output(oDataT1)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:31)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>oDataT1</Name>
-	</Node>
-	<Node criticalPaths="[]" group="[]" id="26" isControl="false" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeConstantRawBits">
-		<Output latency="0" name="value" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>{HWOffsetFix:1, 0, UNSIGNED}\n0x1; 1.0</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:32)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Value>1</Value>
-		<HexValue>0x1</HexValue>
-		<NumericValue>1.0</NumericValue>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="29" dst_node_input="a" src_node_id="26" src_node_output="value" />
-	<Node criticalPaths="[]" group="[]" id="27" isControl="true" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeInputMappedReg">
-		<Output latency="0" name="io_oDataT2_force_disabled" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>Scalar input (io_oDataT2_force_disabled)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:32)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>io_oDataT2_force_disabled</Name>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="28" dst_node_input="a" src_node_id="27" src_node_output="io_oDataT2_force_disabled" />
-	<Node criticalPaths="[]" group="[]" id="28" isControl="true" isVisible="false" pipelineFactor="0.0" powerUsage="N/A" type="NodeNot">
-		<Input name="a" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Output latency="0" name="result" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>~</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:32)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="29" dst_node_input="b" src_node_id="28" src_node_output="result" />
-	<Node criticalPaths="[]" group="[]" id="29" isControl="false" isVisible="false" pipelineFactor="0.0" powerUsage="N/A" type="NodeAnd">
-		<Input name="a" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Input name="b" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Output latency="0" name="result" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>&amp;</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="1" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:32)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="30" dst_node_input="output_control" src_node_id="29" src_node_output="result" />
-	<Node criticalPaths="[]" group="[]" id="6" isControl="true" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeInputMappedReg">
-		<Output latency="0" name="io_inAT2_force_disabled" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>Scalar input (io_inAT2_force_disabled)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:19)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>io_inAT2_force_disabled</Name>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="7" dst_node_input="a" src_node_id="6" src_node_output="io_inAT2_force_disabled" />
-	<Node criticalPaths="[]" group="[]" id="7" isControl="true" isVisible="false" pipelineFactor="0.0" powerUsage="N/A" type="NodeNot">
-		<Input name="a" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Output latency="0" name="result" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>~</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:19)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="8" dst_node_input="enable" src_node_id="7" src_node_output="result" />
-	<Node criticalPaths="[]" group="[]" id="8" isControl="false" isVisible="true" pipelineFactor="1.0" powerUsage="N/A" type="NodeInput">
-		<Input name="enable" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Output latency="5" name="data" type="dfeOffsetFix(32, 0, TWOSCOMPLEMENT)" />
-		<Text>Input(inAT2)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:19)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>inAT2</Name>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="19" dst_node_input="a" src_node_id="8" src_node_output="data" />
-	<Node criticalPaths="[]" group="[]" id="9" isControl="true" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeInputMappedReg">
-		<Output latency="0" name="io_inBT2_force_disabled" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>Scalar input (io_inBT2_force_disabled)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:20)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>io_inBT2_force_disabled</Name>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="10" dst_node_input="a" src_node_id="9" src_node_output="io_inBT2_force_disabled" />
-	<Node criticalPaths="[]" group="[]" id="10" isControl="true" isVisible="false" pipelineFactor="0.0" powerUsage="N/A" type="NodeNot">
-		<Input name="a" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Output latency="0" name="result" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>~</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:20)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="11" dst_node_input="enable" src_node_id="10" src_node_output="result" />
-	<Node criticalPaths="[]" group="[]" id="11" isControl="false" isVisible="true" pipelineFactor="1.0" powerUsage="N/A" type="NodeInput">
-		<Input name="enable" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Output latency="5" name="data" type="dfeOffsetFix(32, 0, TWOSCOMPLEMENT)" />
-		<Text>Input(inBT2)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:20)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>inBT2</Name>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="19" dst_node_input="b" src_node_id="11" src_node_output="data" />
-	<Node criticalPaths="[]" group="[]" id="19" isControl="false" isVisible="true" pipelineFactor="1.0" powerUsage="N/A" type="NodeMul">
-		<Input name="a" type="dfeOffsetFix(32, 0, TWOSCOMPLEMENT)" />
-		<Input name="b" type="dfeOffsetFix(32, 0, TWOSCOMPLEMENT)" />
-		<Output latency="6" name="result" type="dfeOffsetFix(32, 0, TWOSCOMPLEMENT)" />
-		<Text>*</Text>
-		<ResourceUsage DSPs="0" FFs="192" FMems="0" LUTs="224" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.types.base.DFEVar.mul(DFEVar.java:1118)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:28)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="30" dst_node_input="data" src_node_id="19" src_node_output="result" />
-	<Node criticalPaths="[]" group="[]" id="30" isControl="false" isVisible="true" pipelineFactor="1.0" powerUsage="N/A" type="NodeOutput">
-		<Input name="output_control" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Input name="data" type="dfeOffsetFix(32, 0, TWOSCOMPLEMENT)" />
-		<Text>Output(oDataT2)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:32)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>oDataT2</Name>
-	</Node>
-	<Node criticalPaths="[]" group="[]" id="31" isControl="false" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeConstantRawBits">
-		<Output latency="0" name="value" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>{HWOffsetFix:1, 0, UNSIGNED}\n0x1; 1.0</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:33)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Value>1</Value>
-		<HexValue>0x1</HexValue>
-		<NumericValue>1.0</NumericValue>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="34" dst_node_input="a" src_node_id="31" src_node_output="value" />
-	<Node criticalPaths="[]" group="[]" id="32" isControl="true" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeInputMappedReg">
-		<Output latency="0" name="io_oDataT3_force_disabled" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>Scalar input (io_oDataT3_force_disabled)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:33)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>io_oDataT3_force_disabled</Name>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="33" dst_node_input="a" src_node_id="32" src_node_output="io_oDataT3_force_disabled" />
-	<Node criticalPaths="[]" group="[]" id="33" isControl="true" isVisible="false" pipelineFactor="0.0" powerUsage="N/A" type="NodeNot">
-		<Input name="a" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Output latency="0" name="result" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>~</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:33)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="34" dst_node_input="b" src_node_id="33" src_node_output="result" />
-	<Node criticalPaths="[]" group="[]" id="34" isControl="false" isVisible="false" pipelineFactor="0.0" powerUsage="N/A" type="NodeAnd">
-		<Input name="a" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Input name="b" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Output latency="0" name="result" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>&amp;</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="1" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:33)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="35" dst_node_input="output_control" src_node_id="34" src_node_output="result" />
-	<Node criticalPaths="[]" group="[]" id="12" isControl="true" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeInputMappedReg">
-		<Output latency="0" name="io_inAT3_force_disabled" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>Scalar input (io_inAT3_force_disabled)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:23)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>io_inAT3_force_disabled</Name>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="13" dst_node_input="a" src_node_id="12" src_node_output="io_inAT3_force_disabled" />
-	<Node criticalPaths="[]" group="[]" id="13" isControl="true" isVisible="false" pipelineFactor="0.0" powerUsage="N/A" type="NodeNot">
-		<Input name="a" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Output latency="0" name="result" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>~</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:23)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="14" dst_node_input="enable" src_node_id="13" src_node_output="result" />
-	<Node criticalPaths="[]" group="[]" id="14" isControl="false" isVisible="true" pipelineFactor="1.0" powerUsage="N/A" type="NodeInput">
-		<Input name="enable" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Output latency="5" name="data" type="dfeOffsetFix(32, 0, TWOSCOMPLEMENT)" />
-		<Text>Input(inAT3)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:23)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>inAT3</Name>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="20" dst_node_input="a" src_node_id="14" src_node_output="data" />
-	<Node criticalPaths="[]" group="[]" id="15" isControl="true" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeInputMappedReg">
-		<Output latency="0" name="io_inBT3_force_disabled" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>Scalar input (io_inBT3_force_disabled)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:24)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>io_inBT3_force_disabled</Name>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="16" dst_node_input="a" src_node_id="15" src_node_output="io_inBT3_force_disabled" />
-	<Node criticalPaths="[]" group="[]" id="16" isControl="true" isVisible="false" pipelineFactor="0.0" powerUsage="N/A" type="NodeNot">
-		<Input name="a" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Output latency="0" name="result" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>~</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:24)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="17" dst_node_input="enable" src_node_id="16" src_node_output="result" />
-	<Node criticalPaths="[]" group="[]" id="17" isControl="false" isVisible="true" pipelineFactor="1.0" powerUsage="N/A" type="NodeInput">
-		<Input name="enable" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Output latency="5" name="data" type="dfeOffsetFix(32, 0, TWOSCOMPLEMENT)" />
-		<Text>Input(inBT3)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:24)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>inBT3</Name>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="20" dst_node_input="b" src_node_id="17" src_node_output="data" />
-	<Node criticalPaths="[]" group="[]" id="20" isControl="false" isVisible="true" pipelineFactor="1.0" powerUsage="N/A" type="NodeAdd">
-		<Input name="a" type="dfeOffsetFix(32, 0, TWOSCOMPLEMENT)" />
-		<Input name="b" type="dfeOffsetFix(32, 0, TWOSCOMPLEMENT)" />
-		<Output latency="1" name="result" type="dfeOffsetFix(32, 0, TWOSCOMPLEMENT)" />
-		<Text>+</Text>
-		<ResourceUsage DSPs="0" FFs="32" FMems="0" LUTs="64" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.types.base.DFEVar.add(DFEVar.java:1010)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:29)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="35" dst_node_input="data" src_node_id="20" src_node_output="result" />
-	<Node criticalPaths="[]" group="[]" id="35" isControl="false" isVisible="true" pipelineFactor="1.0" powerUsage="N/A" type="NodeOutput">
-		<Input name="output_control" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Input name="data" type="dfeOffsetFix(32, 0, TWOSCOMPLEMENT)" />
-		<Text>Output(oDataT3)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.&lt;init&gt;(StreamFMAKernel.maxj:33)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>oDataT3</Name>
-	</Node>
-	<Node criticalPaths="[]" group="[]" id="40" isControl="false" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeConstantRawBits">
-		<Output latency="0" name="value" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>{HWOffsetFix:1, 0, UNSIGNED}\n0x1; 1.0</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Value>1</Value>
-		<HexValue>0x1</HexValue>
-		<NumericValue>1.0</NumericValue>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="41" dst_node_input="load" src_node_id="40" src_node_output="value" />
-	<Node criticalPaths="[]" group="[]" id="36" isControl="false" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeConstantDouble">
-		<Output latency="0" name="value" type="dfeUntypedConst()" />
-		<Text>1.0</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Value>1.0</Value>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="38" dst_node_input="enable" src_node_id="36" src_node_output="value" />
-	<Node criticalPaths="[]" group="[]" id="37" isControl="false" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeConstantRawBits">
-		<Output latency="0" name="value" type="dfeOffsetFix(49, 0, UNSIGNED)" />
-		<Text>{HWOffsetFix:49, 0, UNSIGNED}\n0x1000000000000; 2.81474976710656E14</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Value>1000000000000000000000000000000000000000000000000</Value>
-		<HexValue>0x1000000000000</HexValue>
-		<NumericValue>2.81474976710656E14</NumericValue>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="38" dst_node_input="max" src_node_id="37" src_node_output="value" />
-	<Node criticalPaths="[]" group="[]" id="38" isControl="false" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeCounter">
-		<Input name="enable" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Input name="max" type="dfeOffsetFix(49, 0, UNSIGNED)" />
-		<Output latency="0" name="count" type="dfeOffsetFix(48, 0, UNSIGNED)" />
-		<Output latency="0" name="wrap" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>Counter(NUMERIC_INCREMENTING)\nInc: 1\nReset: 0\nInit: 0</Text>
-		<ResourceUsage DSPs="0" FFs="48" FMems="0" LUTs="48" />
-		<OriginStackTrace>com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Increment>1</Increment>
-		<WrapValue>0</WrapValue>
-		<InitValue>0</InitValue>
-		<CountMode>NUMERIC_INCREMENTING</CountMode>
-		<WrapMode>COUNT_LT_MAX_THEN_WRAP</WrapMode>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="39" dst_node_input="input" src_node_id="38" src_node_output="count" />
-	<Node criticalPaths="[]" group="[]" id="39" isControl="false" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeStreamOffset">
-		<Input name="input" type="dfeOffsetFix(48, 0, UNSIGNED)" />
-		<Output latency="1" name="output" type="dfeOffsetFix(48, 0, UNSIGNED)" />
-		<Text>stream offset: 1</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="41" dst_node_input="data" src_node_id="39" src_node_output="output" />
-	<Node criticalPaths="[]" group="[]" id="41" isControl="false" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeOutputMappedReg">
-		<Input name="load" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Input name="data" type="dfeOffsetFix(48, 0, UNSIGNED)" />
-		<Text>Scalar output (current_run_cycle_count)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>current_run_cycle_count</Name>
-	</Node>
-	<Node criticalPaths="[]" group="[]" id="42" isControl="false" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeConstantDouble">
-		<Output latency="0" name="value" type="dfeUntypedConst()" />
-		<Text>1.0</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Value>1.0</Value>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="44" dst_node_input="enable" src_node_id="42" src_node_output="value" />
-	<Node criticalPaths="[]" group="[]" id="43" isControl="false" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeConstantRawBits">
-		<Output latency="0" name="value" type="dfeOffsetFix(49, 0, UNSIGNED)" />
-		<Text>{HWOffsetFix:49, 0, UNSIGNED}\n0x1000000000000; 2.81474976710656E14</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Value>1000000000000000000000000000000000000000000000000</Value>
-		<HexValue>0x1000000000000</HexValue>
-		<NumericValue>2.81474976710656E14</NumericValue>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="44" dst_node_input="max" src_node_id="43" src_node_output="value" />
-	<Node criticalPaths="[]" group="[]" id="44" isControl="false" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeCounter">
-		<Input name="enable" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Input name="max" type="dfeOffsetFix(49, 0, UNSIGNED)" />
-		<Output latency="0" name="count" type="dfeOffsetFix(48, 0, UNSIGNED)" />
-		<Output latency="0" name="wrap" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>Counter(NUMERIC_INCREMENTING)\nInc: 1\nReset: 0\nInit: 0</Text>
-		<ResourceUsage DSPs="0" FFs="48" FMems="0" LUTs="48" />
-		<OriginStackTrace>com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Increment>1</Increment>
-		<WrapValue>0</WrapValue>
-		<InitValue>0</InitValue>
-		<CountMode>NUMERIC_INCREMENTING</CountMode>
-		<WrapMode>COUNT_LT_MAX_THEN_WRAP</WrapMode>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="47" dst_node_input="a" src_node_id="44" src_node_output="count" />
-	<Node criticalPaths="[]" group="[]" id="46" isControl="true" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeInputMappedReg">
-		<Output latency="0" name="run_cycle_count" type="dfeOffsetFix(48, 0, UNSIGNED)" />
-		<Text>Scalar input (run_cycle_count)</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-		<Name>run_cycle_count</Name>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="47" dst_node_input="b" src_node_id="46" src_node_output="run_cycle_count" />
-	<Node criticalPaths="[]" group="[]" id="47" isControl="false" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeEq">
-		<Input name="a" type="dfeOffsetFix(48, 0, UNSIGNED)" />
-		<Input name="b" type="dfeOffsetFix(48, 0, UNSIGNED)" />
-		<Output latency="1" name="result" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>==</Text>
-		<ResourceUsage DSPs="0" FFs="1" FMems="0" LUTs="2" />
-		<OriginStackTrace>com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-	</Node>
-	<Edge criticalPaths="[]" dst_node_id="45" dst_node_input="start" src_node_id="47" src_node_output="result" />
-	<Node criticalPaths="[]" group="[]" id="45" isControl="false" isVisible="false" pipelineFactor="1.0" powerUsage="N/A" type="NodeFlush">
-		<Input name="start" type="dfeOffsetFix(1, 0, UNSIGNED)" />
-		<Text>flush on trigger</Text>
-		<ResourceUsage DSPs="0" FFs="0" FMems="0" LUTs="0" />
-		<OriginStackTrace>com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)
-perfmodels.StreamFMAManager.&lt;init&gt;(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)</OriginStackTrace>
-	</Node>
-</Graph>

tests/StreamFMA_MAX5C_DFE_SIM/scratch/StreamFMA.h

@@ -1,248 +0,0 @@
-/**\file */
-#ifndef SLIC_DECLARATIONS_StreamFMA_H
-#define SLIC_DECLARATIONS_StreamFMA_H
-#include "MaxSLiCInterface.h"
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-#define StreamFMA_DYNAMIC_CLOCKS_ENABLED (0)
-#define StreamFMA_PCIE_ALIGNMENT (16)
-
-
-/*----------------------------------------------------------------------------*/
-/*---------------------------- Interface default -----------------------------*/
-/*----------------------------------------------------------------------------*/
-
-
-
-
-/**
- * \brief Basic static function for the interface 'default'.
- * 
- * \param [in] ticks_StreamFMAKernel The number of ticks for which kernel "StreamFMAKernel" will run.
- * \param [in] instream_inAT1 Stream "inAT1".
- * \param [in] instream_size_inAT1 The size of the stream instream_inAT1 in bytes.
- * \param [in] instream_inBT1 Stream "inBT1".
- * \param [in] instream_size_inBT1 The size of the stream instream_inBT1 in bytes.
- * \param [out] outstream_oDataT3 Stream "oDataT3".
- * \param [in] outstream_size_oDataT3 The size of the stream outstream_oDataT3 in bytes.
- * \param [in] lmem_address_MemoryControllerPro0_inAT2 Linear LMem control for "inAT2" stream: base address, in bytes.
- * \param [in] lmem_arr_size_MemoryControllerPro0_inAT2 Linear LMem control for "inAT2" stream: array size, in bytes.
- * \param [in] lmem_address_MemoryControllerPro0_inAT3 Linear LMem control for "inAT3" stream: base address, in bytes.
- * \param [in] lmem_arr_size_MemoryControllerPro0_inAT3 Linear LMem control for "inAT3" stream: array size, in bytes.
- * \param [in] lmem_address_MemoryControllerPro0_inBT2 Linear LMem control for "inBT2" stream: base address, in bytes.
- * \param [in] lmem_arr_size_MemoryControllerPro0_inBT2 Linear LMem control for "inBT2" stream: array size, in bytes.
- * \param [in] lmem_address_MemoryControllerPro0_inBT3 Linear LMem control for "inBT3" stream: base address, in bytes.
- * \param [in] lmem_arr_size_MemoryControllerPro0_inBT3 Linear LMem control for "inBT3" stream: array size, in bytes.
- * \param [in] lmem_address_MemoryControllerPro0_oDataT1 Linear LMem control for "oDataT1" stream: base address, in bytes.
- * \param [in] lmem_arr_size_MemoryControllerPro0_oDataT1 Linear LMem control for "oDataT1" stream: array size, in bytes.
- * \param [in] lmem_address_MemoryControllerPro0_oDataT2 Linear LMem control for "oDataT2" stream: base address, in bytes.
- * \param [in] lmem_arr_size_MemoryControllerPro0_oDataT2 Linear LMem control for "oDataT2" stream: array size, in bytes.
- */
-void StreamFMA(
-	uint64_t ticks_StreamFMAKernel,
-	const void *instream_inAT1,
-	size_t instream_size_inAT1,
-	const void *instream_inBT1,
-	size_t instream_size_inBT1,
-	void *outstream_oDataT3,
-	size_t outstream_size_oDataT3,
-	size_t lmem_address_MemoryControllerPro0_inAT2,
-	size_t lmem_arr_size_MemoryControllerPro0_inAT2,
-	size_t lmem_address_MemoryControllerPro0_inAT3,
-	size_t lmem_arr_size_MemoryControllerPro0_inAT3,
-	size_t lmem_address_MemoryControllerPro0_inBT2,
-	size_t lmem_arr_size_MemoryControllerPro0_inBT2,
-	size_t lmem_address_MemoryControllerPro0_inBT3,
-	size_t lmem_arr_size_MemoryControllerPro0_inBT3,
-	size_t lmem_address_MemoryControllerPro0_oDataT1,
-	size_t lmem_arr_size_MemoryControllerPro0_oDataT1,
-	size_t lmem_address_MemoryControllerPro0_oDataT2,
-	size_t lmem_arr_size_MemoryControllerPro0_oDataT2);
-
-/**
- * \brief Basic static non-blocking function for the interface 'default'.
- * 
- * Schedule to run on an engine and return immediately.
- * The status of the run can be checked either by ::max_wait or ::max_nowait;
- * note that one of these *must* be called, so that associated memory can be released.
- * 
- * 
- * \param [in] ticks_StreamFMAKernel The number of ticks for which kernel "StreamFMAKernel" will run.
- * \param [in] instream_inAT1 Stream "inAT1".
- * \param [in] instream_size_inAT1 The size of the stream instream_inAT1 in bytes.
- * \param [in] instream_inBT1 Stream "inBT1".
- * \param [in] instream_size_inBT1 The size of the stream instream_inBT1 in bytes.
- * \param [out] outstream_oDataT3 Stream "oDataT3".
- * \param [in] outstream_size_oDataT3 The size of the stream outstream_oDataT3 in bytes.
- * \param [in] lmem_address_MemoryControllerPro0_inAT2 Linear LMem control for "inAT2" stream: base address, in bytes.
- * \param [in] lmem_arr_size_MemoryControllerPro0_inAT2 Linear LMem control for "inAT2" stream: array size, in bytes.
- * \param [in] lmem_address_MemoryControllerPro0_inAT3 Linear LMem control for "inAT3" stream: base address, in bytes.
- * \param [in] lmem_arr_size_MemoryControllerPro0_inAT3 Linear LMem control for "inAT3" stream: array size, in bytes.
- * \param [in] lmem_address_MemoryControllerPro0_inBT2 Linear LMem control for "inBT2" stream: base address, in bytes.
- * \param [in] lmem_arr_size_MemoryControllerPro0_inBT2 Linear LMem control for "inBT2" stream: array size, in bytes.
- * \param [in] lmem_address_MemoryControllerPro0_inBT3 Linear LMem control for "inBT3" stream: base address, in bytes.
- * \param [in] lmem_arr_size_MemoryControllerPro0_inBT3 Linear LMem control for "inBT3" stream: array size, in bytes.
- * \param [in] lmem_address_MemoryControllerPro0_oDataT1 Linear LMem control for "oDataT1" stream: base address, in bytes.
- * \param [in] lmem_arr_size_MemoryControllerPro0_oDataT1 Linear LMem control for "oDataT1" stream: array size, in bytes.
- * \param [in] lmem_address_MemoryControllerPro0_oDataT2 Linear LMem control for "oDataT2" stream: base address, in bytes.
- * \param [in] lmem_arr_size_MemoryControllerPro0_oDataT2 Linear LMem control for "oDataT2" stream: array size, in bytes.
- * \return A handle on the execution status, or NULL in case of error.
- */
-max_run_t *StreamFMA_nonblock(
-	uint64_t ticks_StreamFMAKernel,
-	const void *instream_inAT1,
-	size_t instream_size_inAT1,
-	const void *instream_inBT1,
-	size_t instream_size_inBT1,
-	void *outstream_oDataT3,
-	size_t outstream_size_oDataT3,
-	size_t lmem_address_MemoryControllerPro0_inAT2,
-	size_t lmem_arr_size_MemoryControllerPro0_inAT2,
-	size_t lmem_address_MemoryControllerPro0_inAT3,
-	size_t lmem_arr_size_MemoryControllerPro0_inAT3,
-	size_t lmem_address_MemoryControllerPro0_inBT2,
-	size_t lmem_arr_size_MemoryControllerPro0_inBT2,
-	size_t lmem_address_MemoryControllerPro0_inBT3,
-	size_t lmem_arr_size_MemoryControllerPro0_inBT3,
-	size_t lmem_address_MemoryControllerPro0_oDataT1,
-	size_t lmem_arr_size_MemoryControllerPro0_oDataT1,
-	size_t lmem_address_MemoryControllerPro0_oDataT2,
-	size_t lmem_arr_size_MemoryControllerPro0_oDataT2);
-
-/**
- * \brief Advanced static interface, structure for the engine interface 'default'
- * 
- */
-typedef struct { 
-	uint64_t ticks_StreamFMAKernel; /**<  [in] The number of ticks for which kernel "StreamFMAKernel" will run. */
-	const void *instream_inAT1; /**<  [in] Stream "inAT1". */
-	size_t instream_size_inAT1; /**<  [in] The size of the stream instream_inAT1 in bytes. */
-	const void *instream_inBT1; /**<  [in] Stream "inBT1". */
-	size_t instream_size_inBT1; /**<  [in] The size of the stream instream_inBT1 in bytes. */
-	void *outstream_oDataT3; /**<  [out] Stream "oDataT3". */
-	size_t outstream_size_oDataT3; /**<  [in] The size of the stream outstream_oDataT3 in bytes. */
-	size_t lmem_address_MemoryControllerPro0_inAT2; /**<  [in] Linear LMem control for "inAT2" stream: base address, in bytes. */
-	size_t lmem_arr_size_MemoryControllerPro0_inAT2; /**<  [in] Linear LMem control for "inAT2" stream: array size, in bytes. */
-	size_t lmem_address_MemoryControllerPro0_inAT3; /**<  [in] Linear LMem control for "inAT3" stream: base address, in bytes. */
-	size_t lmem_arr_size_MemoryControllerPro0_inAT3; /**<  [in] Linear LMem control for "inAT3" stream: array size, in bytes. */
-	size_t lmem_address_MemoryControllerPro0_inBT2; /**<  [in] Linear LMem control for "inBT2" stream: base address, in bytes. */
-	size_t lmem_arr_size_MemoryControllerPro0_inBT2; /**<  [in] Linear LMem control for "inBT2" stream: array size, in bytes. */
-	size_t lmem_address_MemoryControllerPro0_inBT3; /**<  [in] Linear LMem control for "inBT3" stream: base address, in bytes. */
-	size_t lmem_arr_size_MemoryControllerPro0_inBT3; /**<  [in] Linear LMem control for "inBT3" stream: array size, in bytes. */
-	size_t lmem_address_MemoryControllerPro0_oDataT1; /**<  [in] Linear LMem control for "oDataT1" stream: base address, in bytes. */
-	size_t lmem_arr_size_MemoryControllerPro0_oDataT1; /**<  [in] Linear LMem control for "oDataT1" stream: array size, in bytes. */
-	size_t lmem_address_MemoryControllerPro0_oDataT2; /**<  [in] Linear LMem control for "oDataT2" stream: base address, in bytes. */
-	size_t lmem_arr_size_MemoryControllerPro0_oDataT2; /**<  [in] Linear LMem control for "oDataT2" stream: array size, in bytes. */
-} StreamFMA_actions_t;
-
-/**
- * \brief Advanced static function for the interface 'default'.
- * 
- * \param [in] engine The engine on which the actions will be executed.
- * \param [in,out] interface_actions Actions to be executed.
- */
-void StreamFMA_run(
-	max_engine_t *engine,
-	StreamFMA_actions_t *interface_actions);
-
-/**
- * \brief Advanced static non-blocking function for the interface 'default'.
- *
- * Schedule the actions to run on the engine and return immediately.
- * The status of the run can be checked either by ::max_wait or ::max_nowait;
- * note that one of these *must* be called, so that associated memory can be released.
- *
- * 
- * \param [in] engine The engine on which the actions will be executed.
- * \param [in] interface_actions Actions to be executed.
- * \return A handle on the execution status of the actions, or NULL in case of error.
- */
-max_run_t *StreamFMA_run_nonblock(
-	max_engine_t *engine,
-	StreamFMA_actions_t *interface_actions);
-
-/**
- * \brief Group run advanced static function for the interface 'default'.
- * 
- * \param [in] group Group to use.
- * \param [in,out] interface_actions Actions to run.
- *
- * Run the actions on the first device available in the group.
- */
-void StreamFMA_run_group(max_group_t *group, StreamFMA_actions_t *interface_actions);
-
-/**
- * \brief Group run advanced static non-blocking function for the interface 'default'.
- * 
- *
- * Schedule the actions to run on the first device available in the group and return immediately.
- * The status of the run must be checked with ::max_wait. 
- * Note that use of ::max_nowait is prohibited with non-blocking running on groups:
- * see the ::max_run_group_nonblock documentation for more explanation.
- *
- * \param [in] group Group to use.
- * \param [in] interface_actions Actions to run.
- * \return A handle on the execution status of the actions, or NULL in case of error.
- */
-max_run_t *StreamFMA_run_group_nonblock(max_group_t *group, StreamFMA_actions_t *interface_actions);
-
-/**
- * \brief Array run advanced static function for the interface 'default'.
- * 
- * \param [in] engarray The array of devices to use.
- * \param [in,out] interface_actions The array of actions to run.
- *
- * Run the array of actions on the array of engines.  The length of interface_actions
- * must match the size of engarray.
- */
-void StreamFMA_run_array(max_engarray_t *engarray, StreamFMA_actions_t *interface_actions[]);
-
-/**
- * \brief Array run advanced static non-blocking function for the interface 'default'.
- * 
- *
- * Schedule to run the array of actions on the array of engines, and return immediately.
- * The length of interface_actions must match the size of engarray.
- * The status of the run can be checked either by ::max_wait or ::max_nowait;
- * note that one of these *must* be called, so that associated memory can be released.
- *
- * \param [in] engarray The array of devices to use.
- * \param [in] interface_actions The array of actions to run.
- * \return A handle on the execution status of the actions, or NULL in case of error.
- */
-max_run_t *StreamFMA_run_array_nonblock(max_engarray_t *engarray, StreamFMA_actions_t *interface_actions[]);
-
-/**
- * \brief Converts a static-interface action struct into a dynamic-interface max_actions_t struct.
- *
- * Note that this is an internal utility function used by other functions in the static interface.
- *
- * \param [in] maxfile The maxfile to use.
- * \param [in] interface_actions The interface-specific actions to run.
- * \return The dynamic-interface actions to run, or NULL in case of error.
- */
-max_actions_t* StreamFMA_convert(max_file_t *maxfile, StreamFMA_actions_t *interface_actions);
-
-/**
- * \brief Initialise a maxfile.
- */
-max_file_t* StreamFMA_init(void);
-
-/* Error handling functions */
-int StreamFMA_has_errors(void);
-const char* StreamFMA_get_errors(void);
-void StreamFMA_clear_errors(void);
-/* Free statically allocated maxfile data */
-void StreamFMA_free(void);
-/* returns: -1 = error running command; 0 = no error reported */
-int StreamFMA_simulator_start(void);
-/* returns: -1 = error running command; 0 = no error reported */
-int StreamFMA_simulator_stop(void);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-#endif /* SLIC_DECLARATIONS_StreamFMA_H */
-

tests/StreamFMA_MAX5C_DFE_SIM/scratch/StreamFMAKernel.graphs

@@ -1,22 +0,0 @@
-Tue Jan 28 16:01:05 CET 2020
-StreamFMAKernel
-original
-StreamFMAKernel_original.dot
-pre_dsp_extraction
-StreamFMAKernel_pre_dsp_extraction.dot
-post_dsp_extraction
-StreamFMAKernel_post_dsp_extraction.dot
-post_tri_add_extraction
-StreamFMAKernel_post_tri_add_extraction.dot
-pre_condadd_extraction
-StreamFMAKernel_pre_condadd_extraction.dot
-optimised
-StreamFMAKernel_optimised.dot
-tapnfold_1
-StreamFMAKernel_tapnfold_1.dot
-validated_fifos
-StreamFMAKernel_validated_fifos.dot
-tapnfold_2
-StreamFMAKernel_tapnfold_2.dot
-final
-StreamFMAKernel_final.dot

tests/StreamFMA_MAX5C_DFE_SIM/scratch/StreamFMAKernel_Configuration.txt

@@ -1,61 +0,0 @@
-KernelConfiguration.additionalInputPipelining = 64                                          [Init: 64]
-KernelConfiguration.allowDSPCascading = true                                                [Init: true]
-KernelConfiguration.allowInputsOutputsBeforeFlushNode = false                               [Init: false]
-KernelConfiguration.allowZeroLatencyNodeHold = false                                        [Init: false]
-KernelConfiguration.bramBitsThreshold = 2080                                                [Init: 2080]
-KernelConfiguration.buildTarget = MAXCOMPILERSIM_HOST_DRIVEN                                [Init: NONE, change: MAXCOMPILERSIM_HOST_DRIVEN]
-KernelConfiguration.cePipelining = 2                                                        [Init: 2]
-KernelConfiguration.clockPhaseBalanceThreshold = 0.1                                        [Init: 0.1]
-KernelConfiguration.clockPhasingRetries = 50                                                [Init: 50]
-KernelConfiguration.constantMultiplicationWithShiftAddThreshold = 3                         [Init: 3]
-KernelConfiguration.dumpNeighboursString =                                                  [Init: ]
-KernelConfiguration.enableCeReplication = true                                              [Init: true]
-KernelConfiguration.enableClockPhasePartitioning = false                                    [Init: false]
-KernelConfiguration.enableDebugIOControlRegs = true                                         [Init: true]
-KernelConfiguration.enableDummyBuild = false                                                [Init: false]
-KernelConfiguration.enableKernelProfiler = false                                            [Init: false]
-KernelConfiguration.enablePipelinedComputeController = false                                [Init: false]
-KernelConfiguration.enableShadowRegister = false                                            [Init: false]
-KernelConfiguration.enableSmartKernelControl = false                                        [Init: false]
-KernelConfiguration.fifoSrlRegisterStages = 1                                               [Init: 1]
-KernelConfiguration.flushOnInputDataCongtiguous = false                                     [Init: false]
-KernelConfiguration.hardwareDebugDepth = 512                                                [Init: 512]
-KernelConfiguration.hwHierarchyMode = UNSET                                                 [Init: UNSET]
-KernelConfiguration.latencyAnnotation = true                                                [Init: true]
-KernelConfiguration.latencyAnnotationAll = true                                             [Init: true]
-KernelConfiguration.latencyAnnotationIOs =                                                  [Init: null]
-KernelConfiguration.maxCoalescedFifoWidth = 2147483647                                      [Init: 2147483647]
-KernelConfiguration.maxPreAdderFanOut = 1                                                   [Init: 1]
-KernelConfiguration.netlistMode = false                                                     [Init: false]
-KernelConfiguration.numPhotonStateMachines = 1                                              [Init: 1]
-KernelConfiguration.optimizations.ceCounterRegisterDuplication = 1                          [Init: 1]
-KernelConfiguration.optimizations.conditionalArithmetic = true                              [Init: true]
-KernelConfiguration.optimizations.counterChainWrapPipelining = 0                            [Init: 0]
-KernelConfiguration.optimizations.dspAddChain = OPTIMISE                                    [Init: null, change: OPTIMISE]
-KernelConfiguration.optimizations.enableActiveFanoutReduction = false                       [Init: false]
-KernelConfiguration.optimizations.enableBUFGCE = false                                      [Init: false]
-KernelConfiguration.optimizations.enableBetterInputRegistering = false                      [Init: false]
-KernelConfiguration.optimizations.enableBetterRegistering = false                           [Init: false]
-KernelConfiguration.optimizations.enableFIFOCoalescingAcrossPlacementConstraints = false    [Init: false]
-KernelConfiguration.optimizations.enableFifoCoalescing = true                               [Init: true]
-KernelConfiguration.optimizations.enableIntegratedRounding = false                          [Init: false]
-KernelConfiguration.optimizations.enableMappedMemoryHostReadBack = true                     [Init: true]
-KernelConfiguration.optimizations.enableMultiCycleReset = false                             [Init: false]
-KernelConfiguration.optimizations.enablePowerTwoFloatMult = true                            [Init: true]
-KernelConfiguration.optimizations.enableRedundantNodeDeletion = true                        [Init: true]
-KernelConfiguration.optimizations.enableStateMachineRegisterMerging = true                  [Init: true]
-KernelConfiguration.optimizations.inlining = false                                          [Init: false]
-KernelConfiguration.optimizations.inputFlushDistanceFactor = 0                              [Init: 0]
-KernelConfiguration.optimizations.minimumStaticFIFOSplitDepth = 1                           [Init: 1]
-KernelConfiguration.optimizations.optimizationTechnique = DEFAULT                           [Init: DEFAULT]
-KernelConfiguration.optimizations.preserveNodeRegisters = true                              [Init: true]
-KernelConfiguration.optimizations.triAdd = true                                             [Init: true]
-KernelConfiguration.partialReconfBlockName =                                                [Init: ]
-KernelConfiguration.partialReconfMode = false                                               [Init: false]
-KernelConfiguration.partialReconfTemplate = false                                           [Init: false]
-KernelConfiguration.replicateNodeCeLog2NumPartitions = 0                                    [Init: 0]
-KernelConfiguration.romBRAMBitsThreshold = 2080                                             [Init: 2080]
-KernelConfiguration.simulation.ramAddressCollisionBehaviour = EXCEPTION                     [Init: EXCEPTION]
-KernelConfiguration.simulation.ramOutOfBoundsAccessBehaviour = EXCEPTION                    [Init: EXCEPTION]
-KernelConfiguration.simulation.simProgressMessageFrequency = 0                              [Init: 0]
-KernelConfiguration.useAsapScheduler = false                                                [Init: false]

tests/StreamFMA_MAX5C_DFE_SIM/scratch/StreamFMAKernel_CriticalPath_inAT1_to_oDataT1.dot

@@ -1,23 +0,0 @@
-digraph StreamFMAKernel_CriticalPath_inAT1_to_oDataT1{
-	NodeInput2 [color=red, style="bold, filled", fillcolor=yellow, shape=invhouse, label="inAT1\nID: 2"];
-	NodeInput5 [shape=invhouse, label="inBT1\nID: 5"];
-	NodeAdd18 [color=red, style="bold, filled", fillcolor=yellow, label="+\nID: 18"];
-	NodeOutput25 [color=red, style="bold, filled", fillcolor=yellow, shape=house, label="oDataT1\nID: 25"];
-	NodeInput8 [shape=invhouse, label="inAT2\nID: 8"];
-	NodeInput11 [shape=invhouse, label="inBT2\nID: 11"];
-	NodeMul19 [label="*\nID: 19"];
-	NodeOutput30 [shape=house, label="oDataT2\nID: 30"];
-	NodeInput14 [shape=invhouse, label="inAT3\nID: 14"];
-	NodeInput17 [shape=invhouse, label="inBT3\nID: 17"];
-	NodeAdd20 [label="+\nID: 20"];
-	NodeOutput35 [shape=house, label="oDataT3\nID: 35"];
-	NodeInput2 -> NodeAdd18[color=red style=bold photon_data="EDGE,SrcNode:2,SrcNodePort:data"];
-	NodeInput5 -> NodeAdd18[color="/dark28/1" photon_data="EDGE,SrcNode:5,SrcNodePort:data"];
-	NodeAdd18 -> NodeOutput25[color=red style=bold photon_data="EDGE,SrcNode:18,SrcNodePort:result"];
-	NodeInput8 -> NodeMul19[color="/dark28/2" photon_data="EDGE,SrcNode:8,SrcNodePort:data"];
-	NodeInput11 -> NodeMul19[color="/dark28/3" photon_data="EDGE,SrcNode:11,SrcNodePort:data"];
-	NodeMul19 -> NodeOutput30[color="/dark28/4" photon_data="EDGE,SrcNode:19,SrcNodePort:result"];
-	NodeInput14 -> NodeAdd20[color="/dark28/5" photon_data="EDGE,SrcNode:14,SrcNodePort:data"];
-	NodeInput17 -> NodeAdd20[color="/dark28/6" photon_data="EDGE,SrcNode:17,SrcNodePort:data"];
-	NodeAdd20 -> NodeOutput35[color="/dark28/7" photon_data="EDGE,SrcNode:20,SrcNodePort:result"];
-}

tests/StreamFMA_MAX5C_DFE_SIM/scratch/StreamFMAKernel_CriticalPath_inAT2_to_oDataT2.dot

@@ -1,23 +0,0 @@
-digraph StreamFMAKernel_CriticalPath_inAT2_to_oDataT2{
-	NodeInput2 [shape=invhouse, label="inAT1\nID: 2"];
-	NodeInput5 [shape=invhouse, label="inBT1\nID: 5"];
-	NodeAdd18 [label="+\nID: 18"];
-	NodeOutput25 [shape=house, label="oDataT1\nID: 25"];
-	NodeInput8 [color=red, style="bold, filled", fillcolor=yellow, shape=invhouse, label="inAT2\nID: 8"];
-	NodeInput11 [shape=invhouse, label="inBT2\nID: 11"];
-	NodeMul19 [color=red, style="bold, filled", fillcolor=yellow, label="*\nID: 19"];
-	NodeOutput30 [color=red, style="bold, filled", fillcolor=yellow, shape=house, label="oDataT2\nID: 30"];
-	NodeInput14 [shape=invhouse, label="inAT3\nID: 14"];
-	NodeInput17 [shape=invhouse, label="inBT3\nID: 17"];
-	NodeAdd20 [label="+\nID: 20"];
-	NodeOutput35 [shape=house, label="oDataT3\nID: 35"];
-	NodeInput2 -> NodeAdd18[color="/dark28/1" photon_data="EDGE,SrcNode:2,SrcNodePort:data"];
-	NodeInput5 -> NodeAdd18[color="/dark28/2" photon_data="EDGE,SrcNode:5,SrcNodePort:data"];
-	NodeAdd18 -> NodeOutput25[color="/dark28/3" photon_data="EDGE,SrcNode:18,SrcNodePort:result"];
-	NodeInput8 -> NodeMul19[color=red style=bold photon_data="EDGE,SrcNode:8,SrcNodePort:data"];
-	NodeInput11 -> NodeMul19[color="/dark28/4" photon_data="EDGE,SrcNode:11,SrcNodePort:data"];
-	NodeMul19 -> NodeOutput30[color=red style=bold photon_data="EDGE,SrcNode:19,SrcNodePort:result"];
-	NodeInput14 -> NodeAdd20[color="/dark28/5" photon_data="EDGE,SrcNode:14,SrcNodePort:data"];
-	NodeInput17 -> NodeAdd20[color="/dark28/6" photon_data="EDGE,SrcNode:17,SrcNodePort:data"];
-	NodeAdd20 -> NodeOutput35[color="/dark28/7" photon_data="EDGE,SrcNode:20,SrcNodePort:result"];
-}

tests/StreamFMA_MAX5C_DFE_SIM/scratch/StreamFMAKernel_CriticalPath_inAT3_to_oDataT3.dot

@@ -1,23 +0,0 @@
-digraph StreamFMAKernel_CriticalPath_inAT3_to_oDataT3{
-	NodeInput2 [shape=invhouse, label="inAT1\nID: 2"];
-	NodeInput5 [shape=invhouse, label="inBT1\nID: 5"];
-	NodeAdd18 [label="+\nID: 18"];
-	NodeOutput25 [shape=house, label="oDataT1\nID: 25"];
-	NodeInput8 [shape=invhouse, label="inAT2\nID: 8"];
-	NodeInput11 [shape=invhouse, label="inBT2\nID: 11"];
-	NodeMul19 [label="*\nID: 19"];
-	NodeOutput30 [shape=house, label="oDataT2\nID: 30"];
-	NodeInput14 [color=red, style="bold, filled", fillcolor=yellow, shape=invhouse, label="inAT3\nID: 14"];
-	NodeInput17 [shape=invhouse, label="inBT3\nID: 17"];
-	NodeAdd20 [color=red, style="bold, filled", fillcolor=yellow, label="+\nID: 20"];
-	NodeOutput35 [color=red, style="bold, filled", fillcolor=yellow, shape=house, label="oDataT3\nID: 35"];
-	NodeInput2 -> NodeAdd18[color="/dark28/1" photon_data="EDGE,SrcNode:2,SrcNodePort:data"];
-	NodeInput5 -> NodeAdd18[color="/dark28/2" photon_data="EDGE,SrcNode:5,SrcNodePort:data"];
-	NodeAdd18 -> NodeOutput25[color="/dark28/3" photon_data="EDGE,SrcNode:18,SrcNodePort:result"];
-	NodeInput8 -> NodeMul19[color="/dark28/4" photon_data="EDGE,SrcNode:8,SrcNodePort:data"];
-	NodeInput11 -> NodeMul19[color="/dark28/5" photon_data="EDGE,SrcNode:11,SrcNodePort:data"];
-	NodeMul19 -> NodeOutput30[color="/dark28/6" photon_data="EDGE,SrcNode:19,SrcNodePort:result"];
-	NodeInput14 -> NodeAdd20[color=red style=bold photon_data="EDGE,SrcNode:14,SrcNodePort:data"];
-	NodeInput17 -> NodeAdd20[color="/dark28/7" photon_data="EDGE,SrcNode:17,SrcNodePort:data"];
-	NodeAdd20 -> NodeOutput35[color=red style=bold photon_data="EDGE,SrcNode:20,SrcNodePort:result"];
-}

tests/StreamFMA_MAX5C_DFE_SIM/scratch/StreamFMAKernel_CriticalPath_inBT1_to_oDataT1.dot

@@ -1,23 +0,0 @@
-digraph StreamFMAKernel_CriticalPath_inBT1_to_oDataT1{
-	NodeInput2 [shape=invhouse, label="inAT1\nID: 2"];
-	NodeInput5 [color=red, style="bold, filled", fillcolor=yellow, shape=invhouse, label="inBT1\nID: 5"];
-	NodeAdd18 [color=red, style="bold, filled", fillcolor=yellow, label="+\nID: 18"];
-	NodeOutput25 [color=red, style="bold, filled", fillcolor=yellow, shape=house, label="oDataT1\nID: 25"];
-	NodeInput8 [shape=invhouse, label="inAT2\nID: 8"];
-	NodeInput11 [shape=invhouse, label="inBT2\nID: 11"];
-	NodeMul19 [label="*\nID: 19"];
-	NodeOutput30 [shape=house, label="oDataT2\nID: 30"];
-	NodeInput14 [shape=invhouse, label="inAT3\nID: 14"];
-	NodeInput17 [shape=invhouse, label="inBT3\nID: 17"];
-	NodeAdd20 [label="+\nID: 20"];
-	NodeOutput35 [shape=house, label="oDataT3\nID: 35"];
-	NodeInput2 -> NodeAdd18[color="/dark28/1" photon_data="EDGE,SrcNode:2,SrcNodePort:data"];
-	NodeInput5 -> NodeAdd18[color=red style=bold photon_data="EDGE,SrcNode:5,SrcNodePort:data"];
-	NodeAdd18 -> NodeOutput25[color=red style=bold photon_data="EDGE,SrcNode:18,SrcNodePort:result"];
-	NodeInput8 -> NodeMul19[color="/dark28/2" photon_data="EDGE,SrcNode:8,SrcNodePort:data"];
-	NodeInput11 -> NodeMul19[color="/dark28/3" photon_data="EDGE,SrcNode:11,SrcNodePort:data"];
-	NodeMul19 -> NodeOutput30[color="/dark28/4" photon_data="EDGE,SrcNode:19,SrcNodePort:result"];
-	NodeInput14 -> NodeAdd20[color="/dark28/5" photon_data="EDGE,SrcNode:14,SrcNodePort:data"];
-	NodeInput17 -> NodeAdd20[color="/dark28/6" photon_data="EDGE,SrcNode:17,SrcNodePort:data"];
-	NodeAdd20 -> NodeOutput35[color="/dark28/7" photon_data="EDGE,SrcNode:20,SrcNodePort:result"];
-}

tests/StreamFMA_MAX5C_DFE_SIM/scratch/StreamFMAKernel_CriticalPath_inBT2_to_oDataT2.dot

@@ -1,23 +0,0 @@
-digraph StreamFMAKernel_CriticalPath_inBT2_to_oDataT2{
-	NodeInput2 [shape=invhouse, label="inAT1\nID: 2"];
-	NodeInput5 [shape=invhouse, label="inBT1\nID: 5"];
-	NodeAdd18 [label="+\nID: 18"];
-	NodeOutput25 [shape=house, label="oDataT1\nID: 25"];
-	NodeInput8 [shape=invhouse, label="inAT2\nID: 8"];
-	NodeInput11 [color=red, style="bold, filled", fillcolor=yellow, shape=invhouse, label="inBT2\nID: 11"];
-	NodeMul19 [color=red, style="bold, filled", fillcolor=yellow, label="*\nID: 19"];
-	NodeOutput30 [color=red, style="bold, filled", fillcolor=yellow, shape=house, label="oDataT2\nID: 30"];
-	NodeInput14 [shape=invhouse, label="inAT3\nID: 14"];
-	NodeInput17 [shape=invhouse, label="inBT3\nID: 17"];
-	NodeAdd20 [label="+\nID: 20"];
-	NodeOutput35 [shape=house, label="oDataT3\nID: 35"];
-	NodeInput2 -> NodeAdd18[color="/dark28/1" photon_data="EDGE,SrcNode:2,SrcNodePort:data"];
-	NodeInput5 -> NodeAdd18[color="/dark28/2" photon_data="EDGE,SrcNode:5,SrcNodePort:data"];
-	NodeAdd18 -> NodeOutput25[color="/dark28/3" photon_data="EDGE,SrcNode:18,SrcNodePort:result"];
-	NodeInput8 -> NodeMul19[color="/dark28/4" photon_data="EDGE,SrcNode:8,SrcNodePort:data"];
-	NodeInput11 -> NodeMul19[color=red style=bold photon_data="EDGE,SrcNode:11,SrcNodePort:data"];
-	NodeMul19 -> NodeOutput30[color=red style=bold photon_data="EDGE,SrcNode:19,SrcNodePort:result"];
-	NodeInput14 -> NodeAdd20[color="/dark28/5" photon_data="EDGE,SrcNode:14,SrcNodePort:data"];
-	NodeInput17 -> NodeAdd20[color="/dark28/6" photon_data="EDGE,SrcNode:17,SrcNodePort:data"];
-	NodeAdd20 -> NodeOutput35[color="/dark28/7" photon_data="EDGE,SrcNode:20,SrcNodePort:result"];
-}

tests/StreamFMA_MAX5C_DFE_SIM/scratch/StreamFMAKernel_CriticalPath_inBT3_to_oDataT3.dot

@@ -1,23 +0,0 @@
-digraph StreamFMAKernel_CriticalPath_inBT3_to_oDataT3{
-	NodeInput2 [shape=invhouse, label="inAT1\nID: 2"];
-	NodeInput5 [shape=invhouse, label="inBT1\nID: 5"];
-	NodeAdd18 [label="+\nID: 18"];
-	NodeOutput25 [shape=house, label="oDataT1\nID: 25"];
-	NodeInput8 [shape=invhouse, label="inAT2\nID: 8"];
-	NodeInput11 [shape=invhouse, label="inBT2\nID: 11"];
-	NodeMul19 [label="*\nID: 19"];
-	NodeOutput30 [shape=house, label="oDataT2\nID: 30"];
-	NodeInput14 [shape=invhouse, label="inAT3\nID: 14"];
-	NodeInput17 [color=red, style="bold, filled", fillcolor=yellow, shape=invhouse, label="inBT3\nID: 17"];
-	NodeAdd20 [color=red, style="bold, filled", fillcolor=yellow, label="+\nID: 20"];
-	NodeOutput35 [color=red, style="bold, filled", fillcolor=yellow, shape=house, label="oDataT3\nID: 35"];
-	NodeInput2 -> NodeAdd18[color="/dark28/1" photon_data="EDGE,SrcNode:2,SrcNodePort:data"];
-	NodeInput5 -> NodeAdd18[color="/dark28/2" photon_data="EDGE,SrcNode:5,SrcNodePort:data"];
-	NodeAdd18 -> NodeOutput25[color="/dark28/3" photon_data="EDGE,SrcNode:18,SrcNodePort:result"];
-	NodeInput8 -> NodeMul19[color="/dark28/4" photon_data="EDGE,SrcNode:8,SrcNodePort:data"];
-	NodeInput11 -> NodeMul19[color="/dark28/5" photon_data="EDGE,SrcNode:11,SrcNodePort:data"];
-	NodeMul19 -> NodeOutput30[color="/dark28/6" photon_data="EDGE,SrcNode:19,SrcNodePort:result"];
-	NodeInput14 -> NodeAdd20[color="/dark28/7" photon_data="EDGE,SrcNode:14,SrcNodePort:data"];
-	NodeInput17 -> NodeAdd20[color=red style=bold photon_data="EDGE,SrcNode:17,SrcNodePort:data"];
-	NodeAdd20 -> NodeOutput35[color=red style=bold photon_data="EDGE,SrcNode:20,SrcNodePort:result"];
-}

tests/StreamFMA_MAX5C_DFE_SIM/scratch/StreamFMAKernel_FIFOReport.dot

@@ -1,2 +0,0 @@
-digraph fifoReportGraph {
-}

tests/StreamFMA_MAX5C_DFE_SIM/scratch/StreamFMAKernel_FIFOReportSimple.dot

@@ -1,2 +0,0 @@
-digraph fifoReportGraph {
-}

tests/StreamFMA_MAX5C_DFE_SIM/scratch/StreamFMAKernel_FIFOReportTopHitters.txt

@@ -1,8 +0,0 @@
-Top 10 largest FIFOs
-     Costs                                              From                                                To
-
-Top 10 lines with FIFO sinks
-     Costs                                              LineFIFO Count
-
-Top 10 lines with FIFO sources
-     Costs                                              LineFIFO Count

tests/StreamFMA_MAX5C_DFE_SIM/scratch/StreamFMAKernel_IODistances.h

@@ -1,18 +0,0 @@
-X(IO_DISTANCE_INAT1_ODATAT1, 6)
-X(IO_DISTANCE_INAT1_ODATAT2, 11)
-X(IO_DISTANCE_INAT1_ODATAT3, 6)
-X(IO_DISTANCE_INBT1_ODATAT1, 6)
-X(IO_DISTANCE_INBT1_ODATAT2, 11)
-X(IO_DISTANCE_INBT1_ODATAT3, 6)
-X(IO_DISTANCE_INAT2_ODATAT1, 6)
-X(IO_DISTANCE_INAT2_ODATAT2, 11)
-X(IO_DISTANCE_INAT2_ODATAT3, 6)
-X(IO_DISTANCE_INBT2_ODATAT1, 6)
-X(IO_DISTANCE_INBT2_ODATAT2, 11)
-X(IO_DISTANCE_INBT2_ODATAT3, 6)
-X(IO_DISTANCE_INAT3_ODATAT1, 6)
-X(IO_DISTANCE_INAT3_ODATAT2, 11)
-X(IO_DISTANCE_INAT3_ODATAT3, 6)
-X(IO_DISTANCE_INBT3_ODATAT1, 6)
-X(IO_DISTANCE_INBT3_ODATAT2, 11)
-X(IO_DISTANCE_INBT3_ODATAT3, 6)

tests/StreamFMA_MAX5C_DFE_SIM/scratch/StreamFMAKernel_NodeDiary.txt

@@ -1,504 +0,0 @@
-NodeID     : 0
-Node       : Scalar input (io_inAT1_force_disabled)
-Node type  : NodeInputMappedReg
-Creator    : User
-Stack Trace:
-com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:15)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NodeID     : 1
-Node       : ~
-Node type  : NodeNot
-Creator    : User
-Stack Trace:
-com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:15)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NodeID     : 2
-Node       : Input(inAT1)
-Node type  : NodeInput
-Creator    : User
-Stack Trace:
-com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:15)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NodeID     : 3
-Node       : Scalar input (io_inBT1_force_disabled)
-Node type  : NodeInputMappedReg
-Creator    : User
-Stack Trace:
-com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:16)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NodeID     : 4
-Node       : ~
-Node type  : NodeNot
-Creator    : User
-Stack Trace:
-com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:16)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NodeID     : 5
-Node       : Input(inBT1)
-Node type  : NodeInput
-Creator    : User
-Stack Trace:
-com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:16)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NodeID     : 6
-Node       : Scalar input (io_inAT2_force_disabled)
-Node type  : NodeInputMappedReg
-Creator    : User
-Stack Trace:
-com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:19)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NodeID     : 7
-Node       : ~
-Node type  : NodeNot
-Creator    : User
-Stack Trace:
-com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:19)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NodeID     : 8
-Node       : Input(inAT2)
-Node type  : NodeInput
-Creator    : User
-Stack Trace:
-com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:19)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NodeID     : 9
-Node       : Scalar input (io_inBT2_force_disabled)
-Node type  : NodeInputMappedReg
-Creator    : User
-Stack Trace:
-com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:20)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NodeID     : 10
-Node       : ~
-Node type  : NodeNot
-Creator    : User
-Stack Trace:
-com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:20)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NodeID     : 11
-Node       : Input(inBT2)
-Node type  : NodeInput
-Creator    : User
-Stack Trace:
-com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:20)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NodeID     : 12
-Node       : Scalar input (io_inAT3_force_disabled)
-Node type  : NodeInputMappedReg
-Creator    : User
-Stack Trace:
-com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:23)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NodeID     : 13
-Node       : ~
-Node type  : NodeNot
-Creator    : User
-Stack Trace:
-com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:23)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NodeID     : 14
-Node       : Input(inAT3)
-Node type  : NodeInput
-Creator    : User
-Stack Trace:
-com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:23)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NodeID     : 15
-Node       : Scalar input (io_inBT3_force_disabled)
-Node type  : NodeInputMappedReg
-Creator    : User
-Stack Trace:
-com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:24)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NodeID     : 16
-Node       : ~
-Node type  : NodeNot
-Creator    : User
-Stack Trace:
-com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:24)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NodeID     : 17
-Node       : Input(inBT3)
-Node type  : NodeInput
-Creator    : User
-Stack Trace:
-com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.input(IO.java:630)
-perfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:24)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NodeID     : 18
-Node       : +
-Node type  : NodeAdd
-Creator    : User
-Stack Trace:
-com.maxeler.maxcompiler.v2.kernelcompiler.types.base.DFEVar.add(DFEVar.java:1010)
-perfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:27)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NodeID     : 19
-Node       : *
-Node type  : NodeMul
-Creator    : User
-Stack Trace:
-com.maxeler.maxcompiler.v2.kernelcompiler.types.base.DFEVar.mul(DFEVar.java:1118)
-perfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:28)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NodeID     : 20
-Node       : +
-Node type  : NodeAdd
-Creator    : User
-Stack Trace:
-com.maxeler.maxcompiler.v2.kernelcompiler.types.base.DFEVar.add(DFEVar.java:1010)
-perfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:29)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NODE WAS REMOVED!
-NodeID     : 21
-Node       : {HWOffsetFix:1, 0, UNSIGNED}\n0x1; 1.0
-Node type  : NodeConstantRawBits
-Removed by : [OptimiseNodesPass]
-Creator    : User
-Stack Trace:
-com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:31)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NodeID     : 22
-Node       : Scalar input (io_oDataT1_force_disabled)
-Node type  : NodeInputMappedReg
-Creator    : User
-Stack Trace:
-com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:31)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NodeID     : 23
-Node       : ~
-Node type  : NodeNot
-Creator    : User
-Stack Trace:
-com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:31)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NODE WAS REMOVED!
-NodeID     : 24
-Node       : &
-Node type  : NodeAnd
-Removed by : [OptimiseNodesPass]
-Creator    : User
-Stack Trace:
-com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:31)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NodeID     : 25
-Node       : Output(oDataT1)
-Node type  : NodeOutput
-Creator    : User
-Stack Trace:
-com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:31)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NODE WAS REMOVED!
-NodeID     : 26
-Node       : {HWOffsetFix:1, 0, UNSIGNED}\n0x1; 1.0
-Node type  : NodeConstantRawBits
-Removed by : [OptimiseNodesPass]
-Creator    : User
-Stack Trace:
-com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:32)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NodeID     : 27
-Node       : Scalar input (io_oDataT2_force_disabled)
-Node type  : NodeInputMappedReg
-Creator    : User
-Stack Trace:
-com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:32)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NodeID     : 28
-Node       : ~
-Node type  : NodeNot
-Creator    : User
-Stack Trace:
-com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:32)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NODE WAS REMOVED!
-NodeID     : 29
-Node       : &
-Node type  : NodeAnd
-Removed by : [OptimiseNodesPass]
-Creator    : User
-Stack Trace:
-com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:32)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NodeID     : 30
-Node       : Output(oDataT2)
-Node type  : NodeOutput
-Creator    : User
-Stack Trace:
-com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:32)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NODE WAS REMOVED!
-NodeID     : 31
-Node       : {HWOffsetFix:1, 0, UNSIGNED}\n0x1; 1.0
-Node type  : NodeConstantRawBits
-Removed by : [OptimiseNodesPass]
-Creator    : User
-Stack Trace:
-com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:33)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NodeID     : 32
-Node       : Scalar input (io_oDataT3_force_disabled)
-Node type  : NodeInputMappedReg
-Creator    : User
-Stack Trace:
-com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:33)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NodeID     : 33
-Node       : ~
-Node type  : NodeNot
-Creator    : User
-Stack Trace:
-com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:33)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NODE WAS REMOVED!
-NodeID     : 34
-Node       : &
-Node type  : NodeAnd
-Removed by : [OptimiseNodesPass]
-Creator    : User
-Stack Trace:
-com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:33)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NodeID     : 35
-Node       : Output(oDataT3)
-Node type  : NodeOutput
-Creator    : User
-Stack Trace:
-com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.core.IO.output(IO.java:836)
-perfmodels.StreamFMAKernel.<init>(StreamFMAKernel.maxj:33)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NODE WAS REMOVED!
-NodeID     : 36
-Node       : 1.0
-Node type  : NodeConstantDouble
-Removed by : [RemoveUntypedConstants]
-Creator    : User
-Stack Trace:
-com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-Led to:
-  NodeID     : 50
-  Node       : {HWOffsetFix:1, 0, UNSIGNED}\n0x1; 1.0
-  Node type  : NodeConstantRawBits
-  Creator    : RemoveUntypedConstants
-
-------------
-NodeID     : 37
-Node       : {HWOffsetFix:49, 0, UNSIGNED}\n0x1000000000000; 2.81474976710656E14
-Node type  : NodeConstantRawBits
-Creator    : User
-Stack Trace:
-com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NodeID     : 38
-Node       : Counter(NUMERIC_INCREMENTING)\nInc: 1\nReset: 0\nInit: 0
-Node type  : NodeCounter
-Creator    : User
-Stack Trace:
-com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NodeID     : 39
-Node       : stream offset: 1
-Node type  : NodeStreamOffset
-Creator    : User
-Stack Trace:
-com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NodeID     : 40
-Node       : {HWOffsetFix:1, 0, UNSIGNED}\n0x1; 1.0
-Node type  : NodeConstantRawBits
-Creator    : User
-Stack Trace:
-com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NodeID     : 41
-Node       : Scalar output (current_run_cycle_count)
-Node type  : NodeOutputMappedReg
-Creator    : User
-Stack Trace:
-com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NODE WAS REMOVED!
-NodeID     : 42
-Node       : 1.0
-Node type  : NodeConstantDouble
-Removed by : [RemoveUntypedConstants]
-Creator    : User
-Stack Trace:
-com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-Led to:
-  NodeID     : 49
-  Node       : {HWOffsetFix:1, 0, UNSIGNED}\n0x1; 1.0
-  Node type  : NodeConstantRawBits
-  Creator    : RemoveUntypedConstants
-
-------------
-NodeID     : 43
-Node       : {HWOffsetFix:49, 0, UNSIGNED}\n0x1000000000000; 2.81474976710656E14
-Node type  : NodeConstantRawBits
-Creator    : User
-Stack Trace:
-com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NodeID     : 44
-Node       : Counter(NUMERIC_INCREMENTING)\nInc: 1\nReset: 0\nInit: 0
-Node type  : NodeCounter
-Creator    : User
-Stack Trace:
-com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NodeID     : 45
-Node       : flush on trigger
-Node type  : NodeFlush
-Creator    : User
-Stack Trace:
-com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NodeID     : 46
-Node       : Scalar input (run_cycle_count)
-Node type  : NodeInputMappedReg
-Creator    : User
-Stack Trace:
-com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-------------
-NODE WAS REMOVED!
-NodeID     : 47
-Node       : ==
-Node type  : NodeEq
-Removed by : [OptimiseNodesPass]
-Creator    : User
-Stack Trace:
-com.maxeler.platform.max5.manager.Max5ManagerBase.addKernel(Unknown Source)
-perfmodels.StreamFMAManager.<init>(StreamFMAManager.maxj:22)
-perfmodels.StreamFMAManager.main(StreamFMAManager.maxj:59)
-Led to:
-  NodeID     : 48
-  Node       : ==
-  Node type  : NodeEqInlined
-  Creator    : OptimiseNodesPass
-
-------------

tests/StreamFMA_MAX5C_DFE_SIM/scratch/StreamFMAKernel_NodeStallScopeLog.txt

@@ -1,43 +0,0 @@
-              NodeID Stall origin Node ID
-                  22                 none
-                  23                 none
-                   0                 none
-                   1                 none
-                   2                 none
-                   3                 none
-                   4                 none
-                   5                 none
-                  18                 none
-                  25                 none
-                  27                 none
-                  28                 none
-                   6                 none
-                   7                 none
-                   8                 none
-                   9                 none
-                  10                 none
-                  11                 none
-                  19                 none
-                  30                 none
-                  32                 none
-                  33                 none
-                  12                 none
-                  13                 none
-                  14                 none
-                  15                 none
-                  16                 none
-                  17                 none
-                  20                 none
-                  35                 none
-                  40                 none
-                  50                 none
-                  37                 none
-                  38                 none
-                  39                 none
-                  41                 none
-                  49                 none
-                  43                 none
-                  44                 none
-                  46                 none
-                  48                 none
-                  45                 none

tests/StreamFMA_MAX5C_DFE_SIM/scratch/StreamFMAKernel_final.dot

@@ -1,23 +0,0 @@
-digraph StreamFMAKernel_final{
-	NodeInput2 [shape=invhouse, label="inAT1\nID: 2"];
-	NodeInput5 [shape=invhouse, label="inBT1\nID: 5"];
-	NodeAdd18 [label="+\nID: 18"];
-	NodeOutput25 [shape=house, label="oDataT1\nID: 25"];
-	NodeInput8 [shape=invhouse, label="inAT2\nID: 8"];
-	NodeInput11 [shape=invhouse, label="inBT2\nID: 11"];
-	NodeMul19 [label="*\nID: 19"];
-	NodeOutput30 [shape=house, label="oDataT2\nID: 30"];
-	NodeInput14 [shape=invhouse, label="inAT3\nID: 14"];
-	NodeInput17 [shape=invhouse, label="inBT3\nID: 17"];
-	NodeAdd20 [label="+\nID: 20"];
-	NodeOutput35 [shape=house, label="oDataT3\nID: 35"];
-	NodeInput2 -> NodeAdd18[color="/dark28/1" photon_data="EDGE,SrcNode:2,SrcNodePort:data"];
-	NodeInput5 -> NodeAdd18[color="/dark28/2" photon_data="EDGE,SrcNode:5,SrcNodePort:data"];
-	NodeAdd18 -> NodeOutput25[color="/dark28/3" photon_data="EDGE,SrcNode:18,SrcNodePort:result"];
-	NodeInput8 -> NodeMul19[color="/dark28/4" photon_data="EDGE,SrcNode:8,SrcNodePort:data"];
-	NodeInput11 -> NodeMul19[color="/dark28/5" photon_data="EDGE,SrcNode:11,SrcNodePort:data"];
-	NodeMul19 -> NodeOutput30[color="/dark28/6" photon_data="EDGE,SrcNode:19,SrcNodePort:result"];
-	NodeInput14 -> NodeAdd20[color="/dark28/7" photon_data="EDGE,SrcNode:14,SrcNodePort:data"];
-	NodeInput17 -> NodeAdd20[color="/dark28/8" photon_data="EDGE,SrcNode:17,SrcNodePort:data"];
-	NodeAdd20 -> NodeOutput35[color="/dark28/1" photon_data="EDGE,SrcNode:20,SrcNodePort:result"];
-}

tests/StreamFMA_MAX5C_DFE_SIM/scratch/StreamFMAKernel_final_graphDump.dat

@@ -1,51 +0,0 @@
-Node: 22
-Node: 23
-Node: 0
-Node: 1
-Node: 2
-Node: 3
-Node: 4
-Node: 5
-Node: 18
-Node: 25
-Node: 27
-Node: 28
-Node: 6
-Node: 7
-Node: 8
-Node: 9
-Node: 10
-Node: 11
-Node: 19
-Node: 30
-Node: 32
-Node: 33
-Node: 12
-Node: 13
-Node: 14
-Node: 15
-Node: 16
-Node: 17
-Node: 20
-Node: 35
-Node: 40
-Node: 50
-Node: 37
-Node: 38
-Node: 39
-Node: 41
-Node: 49
-Node: 43
-Node: 44
-Node: 46
-Node: 48
-Node: 45
-Edge: 2 -> 18
-Edge: 5 -> 18
-Edge: 18 -> 25
-Edge: 8 -> 19
-Edge: 11 -> 19
-Edge: 19 -> 30
-Edge: 14 -> 20
-Edge: 17 -> 20
-Edge: 20 -> 35

tests/StreamFMA_MAX5C_DFE_SIM/scratch/StreamFMAKernel_nodeschedule_firstfifos.csv

@@ -1,18 +0,0 @@
-2,NodeInput,0
-5,NodeInput,0
-18,NodeAdd,0
-25,NodeOutput,0
-8,NodeInput,0
-11,NodeInput,0
-19,NodeMul,0
-30,NodeOutput,0
-14,NodeInput,0
-17,NodeInput,0
-20,NodeAdd,0
-35,NodeOutput,0
-38,NodeCounter,0
-39,NodeStreamOffset,0
-41,NodeOutputMappedReg,0
-44,NodeCounter,0
-48,NodeEqInlined,0
-45,NodeFlush,0

tests/StreamFMA_MAX5C_DFE_SIM/scratch/StreamFMAKernel_nodeschedule_firstpass.csv

@@ -1,18 +0,0 @@
-2,NodeInput,0
-5,NodeInput,0
-18,NodeAdd,0
-25,NodeOutput,0
-8,NodeInput,0
-11,NodeInput,0
-19,NodeMul,0
-30,NodeOutput,0
-14,NodeInput,0
-17,NodeInput,0
-20,NodeAdd,0
-35,NodeOutput,0
-38,NodeCounter,0
-39,NodeStreamOffset,0
-41,NodeOutputMappedReg,0
-44,NodeCounter,0
-48,NodeEqInlined,0
-45,NodeFlush,0

tests/StreamFMA_MAX5C_DFE_SIM/scratch/StreamFMAKernel_nodeschedule_secondpass.csv

@@ -1,18 +0,0 @@
-2,NodeInput,4
-5,NodeInput,4
-18,NodeAdd,9
-25,NodeOutput,10
-8,NodeInput,4
-11,NodeInput,4
-19,NodeMul,9
-30,NodeOutput,15
-14,NodeInput,4
-17,NodeInput,4
-20,NodeAdd,9
-35,NodeOutput,10
-38,NodeCounter,3
-39,NodeStreamOffset,3
-41,NodeOutputMappedReg,4
-44,NodeCounter,0
-48,NodeEqInlined,0
-45,NodeFlush,1

tests/StreamFMA_MAX5C_DFE_SIM/scratch/StreamFMAKernel_optimised.dot

@@ -1,23 +0,0 @@
-digraph StreamFMAKernel_optimised{
-	NodeInput2 [shape=invhouse, label="inAT1\nID: 2"];
-	NodeInput5 [shape=invhouse, label="inBT1\nID: 5"];
-	NodeAdd18 [label="+\nID: 18"];
-	NodeOutput25 [shape=house, label="oDataT1\nID: 25"];
-	NodeInput8 [shape=invhouse, label="inAT2\nID: 8"];
-	NodeInput11 [shape=invhouse, label="inBT2\nID: 11"];
-	NodeMul19 [label="*\nID: 19"];
-	NodeOutput30 [shape=house, label="oDataT2\nID: 30"];
-	NodeInput14 [shape=invhouse, label="inAT3\nID: 14"];
-	NodeInput17 [shape=invhouse, label="inBT3\nID: 17"];
-	NodeAdd20 [label="+\nID: 20"];
-	NodeOutput35 [shape=house, label="oDataT3\nID: 35"];
-	NodeInput2 -> NodeAdd18[color="/dark28/1" photon_data="EDGE,SrcNode:2,SrcNodePort:data"];
-	NodeInput5 -> NodeAdd18[color="/dark28/2" photon_data="EDGE,SrcNode:5,SrcNodePort:data"];
-	NodeAdd18 -> NodeOutput25[color="/dark28/3" photon_data="EDGE,SrcNode:18,SrcNodePort:result"];
-	NodeInput8 -> NodeMul19[color="/dark28/4" photon_data="EDGE,SrcNode:8,SrcNodePort:data"];
-	NodeInput11 -> NodeMul19[color="/dark28/5" photon_data="EDGE,SrcNode:11,SrcNodePort:data"];
-	NodeMul19 -> NodeOutput30[color="/dark28/6" photon_data="EDGE,SrcNode:19,SrcNodePort:result"];
-	NodeInput14 -> NodeAdd20[color="/dark28/7" photon_data="EDGE,SrcNode:14,SrcNodePort:data"];
-	NodeInput17 -> NodeAdd20[color="/dark28/8" photon_data="EDGE,SrcNode:17,SrcNodePort:data"];
-	NodeAdd20 -> NodeOutput35[color="/dark28/1" photon_data="EDGE,SrcNode:20,SrcNodePort:result"];
-}

tests/StreamFMA_MAX5C_DFE_SIM/scratch/StreamFMAKernel_original.dot

@@ -1,23 +0,0 @@
-digraph StreamFMAKernel_original{
-	NodeInput2 [shape=invhouse, label="inAT1\nID: 2"];
-	NodeInput5 [shape=invhouse, label="inBT1\nID: 5"];
-	NodeAdd18 [label="+\nID: 18"];
-	NodeOutput25 [shape=house, label="oDataT1\nID: 25"];
-	NodeInput8 [shape=invhouse, label="inAT2\nID: 8"];
-	NodeInput11 [shape=invhouse, label="inBT2\nID: 11"];
-	NodeMul19 [label="*\nID: 19"];
-	NodeOutput30 [shape=house, label="oDataT2\nID: 30"];
-	NodeInput14 [shape=invhouse, label="inAT3\nID: 14"];
-	NodeInput17 [shape=invhouse, label="inBT3\nID: 17"];
-	NodeAdd20 [label="+\nID: 20"];
-	NodeOutput35 [shape=house, label="oDataT3\nID: 35"];
-	NodeInput2 -> NodeAdd18[color="/dark28/1" photon_data="EDGE,SrcNode:2,SrcNodePort:data"];
-	NodeInput5 -> NodeAdd18[color="/dark28/2" photon_data="EDGE,SrcNode:5,SrcNodePort:data"];
-	NodeAdd18 -> NodeOutput25[color="/dark28/3" photon_data="EDGE,SrcNode:18,SrcNodePort:result"];
-	NodeInput8 -> NodeMul19[color="/dark28/4" photon_data="EDGE,SrcNode:8,SrcNodePort:data"];
-	NodeInput11 -> NodeMul19[color="/dark28/5" photon_data="EDGE,SrcNode:11,SrcNodePort:data"];
-	NodeMul19 -> NodeOutput30[color="/dark28/6" photon_data="EDGE,SrcNode:19,SrcNodePort:result"];
-	NodeInput14 -> NodeAdd20[color="/dark28/7" photon_data="EDGE,SrcNode:14,SrcNodePort:data"];
-	NodeInput17 -> NodeAdd20[color="/dark28/8" photon_data="EDGE,SrcNode:17,SrcNodePort:data"];
-	NodeAdd20 -> NodeOutput35[color="/dark28/1" photon_data="EDGE,SrcNode:20,SrcNodePort:result"];
-}

tests/StreamFMA_MAX5C_DFE_SIM/scratch/StreamFMAKernel_photon_stats.csv

@@ -1,37 +0,0 @@
-
-Pre-schedule statistics
-
-
-Total nodes: 37
-
-Node class;Type;Length;Num
-NodeAdd;{HWOffsetFix:32, 0, TWOSCOMPLEMENT};0;2
-NodeConstantDouble;HWUntypedConst;0;2
-NodeConstantRawBits;{HWOffsetFix:1, 0, UNSIGNED};0;1
-NodeConstantRawBits;{HWOffsetFix:49, 0, UNSIGNED};0;2
-NodeCounter;{HWOffsetFix:48, 0, UNSIGNED};0;2
-NodeEqInlined;{HWOffsetFix:1, 0, UNSIGNED};0;1
-NodeInput;{HWOffsetFix:32, 0, TWOSCOMPLEMENT};0;6
-NodeInputMappedReg;{HWOffsetFix:1, 0, UNSIGNED};0;9
-NodeInputMappedReg;{HWOffsetFix:48, 0, UNSIGNED};0;1
-NodeMul;{HWOffsetFix:32, 0, TWOSCOMPLEMENT};0;1
-NodeNot;{HWOffsetFix:1, 0, UNSIGNED};0;9
-NodeStreamOffset;{HWOffsetFix:48, 0, UNSIGNED};0;1
-
-Final statistics
-
-
-Total nodes: 37
-
-Node class;Type;Length;Num
-NodeAdd;{HWOffsetFix:32, 0, TWOSCOMPLEMENT};0;2
-NodeConstantRawBits;{HWOffsetFix:1, 0, UNSIGNED};0;3
-NodeConstantRawBits;{HWOffsetFix:49, 0, UNSIGNED};0;2
-NodeCounter;{HWOffsetFix:48, 0, UNSIGNED};0;2
-NodeEqInlined;{HWOffsetFix:1, 0, UNSIGNED};0;1
-NodeInput;{HWOffsetFix:32, 0, TWOSCOMPLEMENT};0;6
-NodeInputMappedReg;{HWOffsetFix:1, 0, UNSIGNED};0;9
-NodeInputMappedReg;{HWOffsetFix:48, 0, UNSIGNED};0;1
-NodeMul;{HWOffsetFix:32, 0, TWOSCOMPLEMENT};0;1
-NodeNot;{HWOffsetFix:1, 0, UNSIGNED};0;9
-NodeStreamOffset;{HWOffsetFix:48, 0, UNSIGNED};0;1

tests/StreamFMA_MAX5C_DFE_SIM/scratch/StreamFMAKernel_post_dsp_extraction.dot

@@ -1,23 +0,0 @@
-digraph StreamFMAKernel_post_dsp_extraction{
-	NodeInput2 [shape=invhouse, label="inAT1\nID: 2"];
-	NodeInput5 [shape=invhouse, label="inBT1\nID: 5"];
-	NodeAdd18 [label="+\nID: 18"];
-	NodeOutput25 [shape=house, label="oDataT1\nID: 25"];
-	NodeInput8 [shape=invhouse, label="inAT2\nID: 8"];
-	NodeInput11 [shape=invhouse, label="inBT2\nID: 11"];
-	NodeMul19 [label="*\nID: 19"];
-	NodeOutput30 [shape=house, label="oDataT2\nID: 30"];
-	NodeInput14 [shape=invhouse, label="inAT3\nID: 14"];
-	NodeInput17 [shape=invhouse, label="inBT3\nID: 17"];
-	NodeAdd20 [label="+\nID: 20"];
-	NodeOutput35 [shape=house, label="oDataT3\nID: 35"];
-	NodeInput2 -> NodeAdd18[color="/dark28/1" photon_data="EDGE,SrcNode:2,SrcNodePort:data"];
-	NodeInput5 -> NodeAdd18[color="/dark28/2" photon_data="EDGE,SrcNode:5,SrcNodePort:data"];
-	NodeAdd18 -> NodeOutput25[color="/dark28/3" photon_data="EDGE,SrcNode:18,SrcNodePort:result"];
-	NodeInput8 -> NodeMul19[color="/dark28/4" photon_data="EDGE,SrcNode:8,SrcNodePort:data"];
-	NodeInput11 -> NodeMul19[color="/dark28/5" photon_data="EDGE,SrcNode:11,SrcNodePort:data"];
-	NodeMul19 -> NodeOutput30[color="/dark28/6" photon_data="EDGE,SrcNode:19,SrcNodePort:result"];
-	NodeInput14 -> NodeAdd20[color="/dark28/7" photon_data="EDGE,SrcNode:14,SrcNodePort:data"];
-	NodeInput17 -> NodeAdd20[color="/dark28/8" photon_data="EDGE,SrcNode:17,SrcNodePort:data"];
-	NodeAdd20 -> NodeOutput35[color="/dark28/1" photon_data="EDGE,SrcNode:20,SrcNodePort:result"];
-}

tests/StreamFMA_MAX5C_DFE_SIM/scratch/StreamFMAKernel_post_tri_add_extraction.dot

@@ -1,23 +0,0 @@
-digraph StreamFMAKernel_post_tri_add_extraction{
-	NodeInput2 [shape=invhouse, label="inAT1\nID: 2"];
-	NodeInput5 [shape=invhouse, label="inBT1\nID: 5"];
-	NodeAdd18 [label="+\nID: 18"];
-	NodeOutput25 [shape=house, label="oDataT1\nID: 25"];
-	NodeInput8 [shape=invhouse, label="inAT2\nID: 8"];
-	NodeInput11 [shape=invhouse, label="inBT2\nID: 11"];
-	NodeMul19 [label="*\nID: 19"];
-	NodeOutput30 [shape=house, label="oDataT2\nID: 30"];
-	NodeInput14 [shape=invhouse, label="inAT3\nID: 14"];
-	NodeInput17 [shape=invhouse, label="inBT3\nID: 17"];
-	NodeAdd20 [label="+\nID: 20"];
-	NodeOutput35 [shape=house, label="oDataT3\nID: 35"];
-	NodeInput2 -> NodeAdd18[color="/dark28/1" photon_data="EDGE,SrcNode:2,SrcNodePort:data"];
-	NodeInput5 -> NodeAdd18[color="/dark28/2" photon_data="EDGE,SrcNode:5,SrcNodePort:data"];
-	NodeAdd18 -> NodeOutput25[color="/dark28/3" photon_data="EDGE,SrcNode:18,SrcNodePort:result"];
-	NodeInput8 -> NodeMul19[color="/dark28/4" photon_data="EDGE,SrcNode:8,SrcNodePort:data"];
-	NodeInput11 -> NodeMul19[color="/dark28/5" photon_data="EDGE,SrcNode:11,SrcNodePort:data"];
-	NodeMul19 -> NodeOutput30[color="/dark28/6" photon_data="EDGE,SrcNode:19,SrcNodePort:result"];
-	NodeInput14 -> NodeAdd20[color="/dark28/7" photon_data="EDGE,SrcNode:14,SrcNodePort:data"];
-	NodeInput17 -> NodeAdd20[color="/dark28/8" photon_data="EDGE,SrcNode:17,SrcNodePort:data"];
-	NodeAdd20 -> NodeOutput35[color="/dark28/1" photon_data="EDGE,SrcNode:20,SrcNodePort:result"];
-}

tests/StreamFMA_MAX5C_DFE_SIM/scratch/StreamFMAKernel_pre_condadd_extraction.dot

@@ -1,23 +0,0 @@
-digraph StreamFMAKernel_pre_condadd_extraction{
-	NodeInput2 [shape=invhouse, label="inAT1\nID: 2"];
-	NodeInput5 [shape=invhouse, label="inBT1\nID: 5"];
-	NodeAdd18 [label="+\nID: 18"];
-	NodeOutput25 [shape=house, label="oDataT1\nID: 25"];
-	NodeInput8 [shape=invhouse, label="inAT2\nID: 8"];
-	NodeInput11 [shape=invhouse, label="inBT2\nID: 11"];
-	NodeMul19 [label="*\nID: 19"];
-	NodeOutput30 [shape=house, label="oDataT2\nID: 30"];
-	NodeInput14 [shape=invhouse, label="inAT3\nID: 14"];
-	NodeInput17 [shape=invhouse, label="inBT3\nID: 17"];
-	NodeAdd20 [label="+\nID: 20"];
-	NodeOutput35 [shape=house, label="oDataT3\nID: 35"];
-	NodeInput2 -> NodeAdd18[color="/dark28/1" photon_data="EDGE,SrcNode:2,SrcNodePort:data"];
-	NodeInput5 -> NodeAdd18[color="/dark28/2" photon_data="EDGE,SrcNode:5,SrcNodePort:data"];
-	NodeAdd18 -> NodeOutput25[color="/dark28/3" photon_data="EDGE,SrcNode:18,SrcNodePort:result"];
-	NodeInput8 -> NodeMul19[color="/dark28/4" photon_data="EDGE,SrcNode:8,SrcNodePort:data"];
-	NodeInput11 -> NodeMul19[color="/dark28/5" photon_data="EDGE,SrcNode:11,SrcNodePort:data"];
-	NodeMul19 -> NodeOutput30[color="/dark28/6" photon_data="EDGE,SrcNode:19,SrcNodePort:result"];
-	NodeInput14 -> NodeAdd20[color="/dark28/7" photon_data="EDGE,SrcNode:14,SrcNodePort:data"];
-	NodeInput17 -> NodeAdd20[color="/dark28/8" photon_data="EDGE,SrcNode:17,SrcNodePort:data"];
-	NodeAdd20 -> NodeOutput35[color="/dark28/1" photon_data="EDGE,SrcNode:20,SrcNodePort:result"];
-}

tests/StreamFMA_MAX5C_DFE_SIM/scratch/StreamFMAKernel_pre_dsp_extraction.dot

@@ -1,23 +0,0 @@
-digraph StreamFMAKernel_pre_dsp_extraction{
-	NodeInput2 [shape=invhouse, label="inAT1\nID: 2"];
-	NodeInput5 [shape=invhouse, label="inBT1\nID: 5"];
-	NodeAdd18 [label="+\nID: 18"];
-	NodeOutput25 [shape=house, label="oDataT1\nID: 25"];
-	NodeInput8 [shape=invhouse, label="inAT2\nID: 8"];
-	NodeInput11 [shape=invhouse, label="inBT2\nID: 11"];
-	NodeMul19 [label="*\nID: 19"];
-	NodeOutput30 [shape=house, label="oDataT2\nID: 30"];
-	NodeInput14 [shape=invhouse, label="inAT3\nID: 14"];
-	NodeInput17 [shape=invhouse, label="inBT3\nID: 17"];
-	NodeAdd20 [label="+\nID: 20"];
-	NodeOutput35 [shape=house, label="oDataT3\nID: 35"];
-	NodeInput2 -> NodeAdd18[color="/dark28/1" photon_data="EDGE,SrcNode:2,SrcNodePort:data"];
-	NodeInput5 -> NodeAdd18[color="/dark28/2" photon_data="EDGE,SrcNode:5,SrcNodePort:data"];
-	NodeAdd18 -> NodeOutput25[color="/dark28/3" photon_data="EDGE,SrcNode:18,SrcNodePort:result"];
-	NodeInput8 -> NodeMul19[color="/dark28/4" photon_data="EDGE,SrcNode:8,SrcNodePort:data"];
-	NodeInput11 -> NodeMul19[color="/dark28/5" photon_data="EDGE,SrcNode:11,SrcNodePort:data"];
-	NodeMul19 -> NodeOutput30[color="/dark28/6" photon_data="EDGE,SrcNode:19,SrcNodePort:result"];
-	NodeInput14 -> NodeAdd20[color="/dark28/7" photon_data="EDGE,SrcNode:14,SrcNodePort:data"];
-	NodeInput17 -> NodeAdd20[color="/dark28/8" photon_data="EDGE,SrcNode:17,SrcNodePort:data"];
-	NodeAdd20 -> NodeOutput35[color="/dark28/1" photon_data="EDGE,SrcNode:20,SrcNodePort:result"];
-}

tests/StreamFMA_MAX5C_DFE_SIM/scratch/StreamFMAKernel_schedule_C.csv

@@ -1,34 +0,0 @@
-name,solution
-C0000001,0
-C0000002,0
-C0000003,0
-C0000004,0
-C0000005,0
-C0000006,0
-C0000007,0
-C0000008,0
-C0000009,0
-C0000010,0
-C0000011,0
-C0000012,0
-C0000013,0
-C0000014,0
-C0000015,0
-C0000016,9
-C0000017,4
-C0000018,4
-C0000019,10
-C0000020,9
-C0000021,4
-C0000022,4
-C0000023,15
-C0000024,9
-C0000025,4
-C0000026,4
-C0000027,10
-C0000028,3
-C0000029,3
-C0000030,4
-C0000031,0
-C0000032,0
-C0000033,1

tests/StreamFMA_MAX5C_DFE_SIM/scratch/StreamFMAKernel_schedule_C.stdout.log

@@ -1,55 +0,0 @@
-Welcome to the CBC MILP Solver 
-Version: 2.9.8 
-Build Date: Apr 18 2016 
-
-command line - /opt/Software/maxeler/maxcompiler-2018.3.1/bin/cbc StreamFMAKernel_schedule_C.mps.gz -threads 12 -solve -printi csv -solu StreamFMAKernel_schedule_C.csv (default strategy 1)
-At line 1 NAME           CxSchedule
-At line 2 ROWS
-At line 40 COLUMNS
-At line 99 RHS
-At line 119 BOUNDS
-At line 153 ENDATA
-Problem CxSchedule has 36 rows, 33 columns and 85 elements
-Coin0008I CxSchedule read with 0 errors
-threads was changed from 0 to 12
-Continuous objective value is 0 - 0.00 seconds
-Cgl0003I 0 fixed, 33 tightened bounds, 0 strengthened rows, 0 substitutions
-Cgl0003I 0 fixed, 1 tightened bounds, 0 strengthened rows, 0 substitutions
-Cgl0004I processed model has 36 rows, 31 columns (31 integer (0 of which binary)) and 85 elements
-Cutoff increment increased from 1e-05 to 0.9999
-Cbc0012I Integer solution of 0 found by DiveCoefficient after 0 iterations and 0 nodes (0.01 seconds)
-Cbc0030I Thread 0 used 0 times,  waiting to start 0.0050170422, 0 cpu time, 0 locks, 0 locked, 0 waiting for locks
-Cbc0030I Thread 1 used 0 times,  waiting to start 0.0065350533, 0 cpu time, 0 locks, 0 locked, 0 waiting for locks
-Cbc0030I Thread 2 used 0 times,  waiting to start 0.0062220097, 0 cpu time, 0 locks, 0 locked, 0 waiting for locks
-Cbc0030I Thread 3 used 0 times,  waiting to start 0.0058715343, 0 cpu time, 0 locks, 0 locked, 0 waiting for locks
-Cbc0030I Thread 4 used 0 times,  waiting to start 0.0055239201, 0 cpu time, 0 locks, 0 locked, 0 waiting for locks
-Cbc0030I Thread 5 used 0 times,  waiting to start 0.0051817894, 0 cpu time, 0 locks, 0 locked, 0 waiting for locks
-Cbc0030I Thread 6 used 0 times,  waiting to start 0.0048797131, 0 cpu time, 0 locks, 0 locked, 0 waiting for locks
-Cbc0030I Thread 7 used 0 times,  waiting to start 0.0045642853, 0 cpu time, 0 locks, 0 locked, 0 waiting for locks
-Cbc0030I Thread 8 used 0 times,  waiting to start 0.0042231083, 0 cpu time, 0 locks, 0 locked, 0 waiting for locks
-Cbc0030I Thread 9 used 0 times,  waiting to start 0.0038909912, 0 cpu time, 0 locks, 0 locked, 0 waiting for locks
-Cbc0030I Thread 10 used 0 times,  waiting to start 0.003534317, 0 cpu time, 0 locks, 0 locked, 0 waiting for locks
-Cbc0030I Thread 11 used 0 times,  waiting to start 0.0032083988, 0 cpu time, 0 locks, 0 locked, 0 waiting for locks
-Cbc0030I Main thread 0 waiting for threads,  1 locks, 4.529953e-06 locked, 4.7683716e-07 waiting for locks
-Cbc0001I Search completed - best objective 0, took 0 iterations and 0 nodes (0.01 seconds)
-Cbc0035I Maximum depth 0, 0 variables fixed on reduced cost
-Cuts at root node changed objective from 0 to 0
-Probing was tried 0 times and created 0 cuts of which 0 were active after adding rounds of cuts (0.000 seconds)
-Gomory was tried 0 times and created 0 cuts of which 0 were active after adding rounds of cuts (0.000 seconds)
-Knapsack was tried 0 times and created 0 cuts of which 0 were active after adding rounds of cuts (0.000 seconds)
-Clique was tried 0 times and created 0 cuts of which 0 were active after adding rounds of cuts (0.000 seconds)
-MixedIntegerRounding2 was tried 0 times and created 0 cuts of which 0 were active after adding rounds of cuts (0.000 seconds)
-FlowCover was tried 0 times and created 0 cuts of which 0 were active after adding rounds of cuts (0.000 seconds)
-TwoMirCuts was tried 0 times and created 0 cuts of which 0 were active after adding rounds of cuts (0.000 seconds)
-
-Result - Optimal solution found
-
-Objective value:                0.00000000
-Enumerated nodes:               0
-Total iterations:               0
-Time (CPU seconds):             0.01
-Time (Wallclock seconds):       0.02
-
-Option for printingOptions changed from normal to csv
-Total time (CPU seconds):       0.02   (Wallclock seconds):       0.03
-

tests/StreamFMA_MAX5C_DFE_SIM/scratch/StreamFMAKernel_tapnfold_1.dot

@@ -1,23 +0,0 @@
-digraph StreamFMAKernel_tapnfold_1{
-	NodeInput2 [shape=invhouse, label="inAT1\nID: 2"];
-	NodeInput5 [shape=invhouse, label="inBT1\nID: 5"];
-	NodeAdd18 [label="+\nID: 18"];
-	NodeOutput25 [shape=house, label="oDataT1\nID: 25"];
-	NodeInput8 [shape=invhouse, label="inAT2\nID: 8"];
-	NodeInput11 [shape=invhouse, label="inBT2\nID: 11"];
-	NodeMul19 [label="*\nID: 19"];
-	NodeOutput30 [shape=house, label="oDataT2\nID: 30"];
-	NodeInput14 [shape=invhouse, label="inAT3\nID: 14"];
-	NodeInput17 [shape=invhouse, label="inBT3\nID: 17"];
-	NodeAdd20 [label="+\nID: 20"];
-	NodeOutput35 [shape=house, label="oDataT3\nID: 35"];
-	NodeInput2 -> NodeAdd18[color="/dark28/1" photon_data="EDGE,SrcNode:2,SrcNodePort:data"];
-	NodeInput5 -> NodeAdd18[color="/dark28/2" photon_data="EDGE,SrcNode:5,SrcNodePort:data"];
-	NodeAdd18 -> NodeOutput25[color="/dark28/3" photon_data="EDGE,SrcNode:18,SrcNodePort:result"];
-	NodeInput8 -> NodeMul19[color="/dark28/4" photon_data="EDGE,SrcNode:8,SrcNodePort:data"];
-	NodeInput11 -> NodeMul19[color="/dark28/5" photon_data="EDGE,SrcNode:11,SrcNodePort:data"];
-	NodeMul19 -> NodeOutput30[color="/dark28/6" photon_data="EDGE,SrcNode:19,SrcNodePort:result"];
-	NodeInput14 -> NodeAdd20[color="/dark28/7" photon_data="EDGE,SrcNode:14,SrcNodePort:data"];
-	NodeInput17 -> NodeAdd20[color="/dark28/8" photon_data="EDGE,SrcNode:17,SrcNodePort:data"];
-	NodeAdd20 -> NodeOutput35[color="/dark28/1" photon_data="EDGE,SrcNode:20,SrcNodePort:result"];
-}

tests/StreamFMA_MAX5C_DFE_SIM/scratch/StreamFMAKernel_tapnfold_2.dot

@@ -1,23 +0,0 @@
-digraph StreamFMAKernel_tapnfold_2{
-	NodeInput2 [shape=invhouse, label="inAT1\nID: 2"];
-	NodeInput5 [shape=invhouse, label="inBT1\nID: 5"];
-	NodeAdd18 [label="+\nID: 18"];
-	NodeOutput25 [shape=house, label="oDataT1\nID: 25"];
-	NodeInput8 [shape=invhouse, label="inAT2\nID: 8"];
-	NodeInput11 [shape=invhouse, label="inBT2\nID: 11"];
-	NodeMul19 [label="*\nID: 19"];
-	NodeOutput30 [shape=house, label="oDataT2\nID: 30"];
-	NodeInput14 [shape=invhouse, label="inAT3\nID: 14"];
-	NodeInput17 [shape=invhouse, label="inBT3\nID: 17"];
-	NodeAdd20 [label="+\nID: 20"];
-	NodeOutput35 [shape=house, label="oDataT3\nID: 35"];
-	NodeInput2 -> NodeAdd18[color="/dark28/1" photon_data="EDGE,SrcNode:2,SrcNodePort:data"];
-	NodeInput5 -> NodeAdd18[color="/dark28/2" photon_data="EDGE,SrcNode:5,SrcNodePort:data"];
-	NodeAdd18 -> NodeOutput25[color="/dark28/3" photon_data="EDGE,SrcNode:18,SrcNodePort:result"];
-	NodeInput8 -> NodeMul19[color="/dark28/4" photon_data="EDGE,SrcNode:8,SrcNodePort:data"];
-	NodeInput11 -> NodeMul19[color="/dark28/5" photon_data="EDGE,SrcNode:11,SrcNodePort:data"];
-	NodeMul19 -> NodeOutput30[color="/dark28/6" photon_data="EDGE,SrcNode:19,SrcNodePort:result"];
-	NodeInput14 -> NodeAdd20[color="/dark28/7" photon_data="EDGE,SrcNode:14,SrcNodePort:data"];
-	NodeInput17 -> NodeAdd20[color="/dark28/8" photon_data="EDGE,SrcNode:17,SrcNodePort:data"];
-	NodeAdd20 -> NodeOutput35[color="/dark28/1" photon_data="EDGE,SrcNode:20,SrcNodePort:result"];
-}

tests/StreamFMA_MAX5C_DFE_SIM/scratch/StreamFMAKernel_validated_fifos.dot

@@ -1,23 +0,0 @@
-digraph StreamFMAKernel_validated_fifos{
-	NodeInput2 [shape=invhouse, label="inAT1\nID: 2"];
-	NodeInput5 [shape=invhouse, label="inBT1\nID: 5"];
-	NodeAdd18 [label="+\nID: 18"];
-	NodeOutput25 [shape=house, label="oDataT1\nID: 25"];
-	NodeInput8 [shape=invhouse, label="inAT2\nID: 8"];
-	NodeInput11 [shape=invhouse, label="inBT2\nID: 11"];
-	NodeMul19 [label="*\nID: 19"];
-	NodeOutput30 [shape=house, label="oDataT2\nID: 30"];
-	NodeInput14 [shape=invhouse, label="inAT3\nID: 14"];
-	NodeInput17 [shape=invhouse, label="inBT3\nID: 17"];
-	NodeAdd20 [label="+\nID: 20"];
-	NodeOutput35 [shape=house, label="oDataT3\nID: 35"];
-	NodeInput2 -> NodeAdd18[color="/dark28/1" photon_data="EDGE,SrcNode:2,SrcNodePort:data"];
-	NodeInput5 -> NodeAdd18[color="/dark28/2" photon_data="EDGE,SrcNode:5,SrcNodePort:data"];
-	NodeAdd18 -> NodeOutput25[color="/dark28/3" photon_data="EDGE,SrcNode:18,SrcNodePort:result"];
-	NodeInput8 -> NodeMul19[color="/dark28/4" photon_data="EDGE,SrcNode:8,SrcNodePort:data"];
-	NodeInput11 -> NodeMul19[color="/dark28/5" photon_data="EDGE,SrcNode:11,SrcNodePort:data"];
-	NodeMul19 -> NodeOutput30[color="/dark28/6" photon_data="EDGE,SrcNode:19,SrcNodePort:result"];
-	NodeInput14 -> NodeAdd20[color="/dark28/7" photon_data="EDGE,SrcNode:14,SrcNodePort:data"];
-	NodeInput17 -> NodeAdd20[color="/dark28/8" photon_data="EDGE,SrcNode:17,SrcNodePort:data"];
-	NodeAdd20 -> NodeOutput35[color="/dark28/1" photon_data="EDGE,SrcNode:20,SrcNodePort:result"];
-}

tests/StreamFMA_MAX5C_DFE_SIM/scratch/StreamWrapperRegs.info

@@ -1,144 +0,0 @@
-ADDRGEN_CMD_MEMORYCONTROLLERPRO0_ODATAT2 version:0,000,instance:0
-	AGEN_ADDR_EN base:0x0,width:1,bytemask:0x1
-		BITS width:1,mask:0x1
-	AGEN_BLOCKSIZE_X base:0x1,width:33,bytemask:0x1f
-		BITS width:33,mask:0xffffffff
-	AGEN_CMDSIZE base:0x6,width:8,bytemask:0x1
-		BITS width:8,mask:0xff
-	AGEN_OFFSET_0 base:0x7,width:31,bytemask:0xf
-		BITS width:31,mask:0x7fffffff
-	AGEN_START_X_ADDR base:0xb,width:32,bytemask:0xf
-		BITS width:32,mask:0xffffffff
-	AGEN_WRAP_X base:0xf,width:32,bytemask:0xf
-		BITS width:32,mask:0xffffffff
-ADDRGEN_CMD_MEMORYCONTROLLERPRO0_ODATAT1 version:0,000,instance:0
-	AGEN_ADDR_EN base:0x13,width:1,bytemask:0x1
-		BITS width:1,mask:0x1
-	AGEN_BLOCKSIZE_X base:0x14,width:33,bytemask:0x1f
-		BITS width:33,mask:0xffffffff
-	AGEN_CMDSIZE base:0x19,width:8,bytemask:0x1
-		BITS width:8,mask:0xff
-	AGEN_OFFSET_0 base:0x1a,width:31,bytemask:0xf
-		BITS width:31,mask:0x7fffffff
-	AGEN_START_X_ADDR base:0x1e,width:32,bytemask:0xf
-		BITS width:32,mask:0xffffffff
-	AGEN_WRAP_X base:0x22,width:32,bytemask:0xf
-		BITS width:32,mask:0xffffffff
-ADDRGEN_CMD_MEMORYCONTROLLERPRO0_INBT2 version:0,000,instance:0
-	AGEN_ADDR_EN base:0x26,width:1,bytemask:0x1
-		BITS width:1,mask:0x1
-	AGEN_BLOCKSIZE_X base:0x27,width:33,bytemask:0x1f
-		BITS width:33,mask:0xffffffff
-	AGEN_CMDSIZE base:0x2c,width:8,bytemask:0x1
-		BITS width:8,mask:0xff
-	AGEN_OFFSET_0 base:0x2d,width:31,bytemask:0xf
-		BITS width:31,mask:0x7fffffff
-	AGEN_START_X_ADDR base:0x31,width:32,bytemask:0xf
-		BITS width:32,mask:0xffffffff
-	AGEN_WRAP_X base:0x35,width:32,bytemask:0xf
-		BITS width:32,mask:0xffffffff
-ADDRGEN_CMD_MEMORYCONTROLLERPRO0_INAT3 version:0,000,instance:0
-	AGEN_ADDR_EN base:0x39,width:1,bytemask:0x1
-		BITS width:1,mask:0x1
-	AGEN_BLOCKSIZE_X base:0x3a,width:33,bytemask:0x1f
-		BITS width:33,mask:0xffffffff
-	AGEN_CMDSIZE base:0x3f,width:8,bytemask:0x1
-		BITS width:8,mask:0xff
-	AGEN_OFFSET_0 base:0x40,width:31,bytemask:0xf
-		BITS width:31,mask:0x7fffffff
-	AGEN_START_X_ADDR base:0x44,width:32,bytemask:0xf
-		BITS width:32,mask:0xffffffff
-	AGEN_WRAP_X base:0x48,width:32,bytemask:0xf
-		BITS width:32,mask:0xffffffff
-ADDRGEN_CMD_MEMORYCONTROLLERPRO0_INBT3 version:0,000,instance:0
-	AGEN_ADDR_EN base:0x4c,width:1,bytemask:0x1
-		BITS width:1,mask:0x1
-	AGEN_BLOCKSIZE_X base:0x4d,width:33,bytemask:0x1f
-		BITS width:33,mask:0xffffffff
-	AGEN_CMDSIZE base:0x52,width:8,bytemask:0x1
-		BITS width:8,mask:0xff
-	AGEN_OFFSET_0 base:0x53,width:31,bytemask:0xf
-		BITS width:31,mask:0x7fffffff
-	AGEN_START_X_ADDR base:0x57,width:32,bytemask:0xf
-		BITS width:32,mask:0xffffffff
-	AGEN_WRAP_X base:0x5b,width:32,bytemask:0xf
-		BITS width:32,mask:0xffffffff
-ADDRGEN_CMD_MEMORYCONTROLLERPRO0_INAT2 version:0,000,instance:0
-	AGEN_ADDR_EN base:0x5f,width:1,bytemask:0x1
-		BITS width:1,mask:0x1
-	AGEN_BLOCKSIZE_X base:0x60,width:33,bytemask:0x1f
-		BITS width:33,mask:0xffffffff
-	AGEN_CMDSIZE base:0x65,width:8,bytemask:0x1
-		BITS width:8,mask:0xff
-	AGEN_OFFSET_0 base:0x66,width:31,bytemask:0xf
-		BITS width:31,mask:0x7fffffff
-	AGEN_START_X_ADDR base:0x6a,width:32,bytemask:0xf
-		BITS width:32,mask:0xffffffff
-	AGEN_WRAP_X base:0x6e,width:32,bytemask:0xf
-		BITS width:32,mask:0xffffffff
-MEMORYCONTROLLERPRO0 version:0,000,instance:0
-	MCP_INT_DISABLE_OR base:0x72,width:6,bytemask:0x1
-		BITS width:6,mask:0x3f
-	MCP_INT_ENABLE_AND base:0x73,width:6,bytemask:0x1
-		BITS width:6,mask:0x3f
-STREAMFMAKERNEL version:0,000,instance:0
-	IO_INAT1_FORCE_DISABLED base:0x74,width:1,bytemask:0x1
-		BITS width:1,mask:0x1
-	IO_INBT1_FORCE_DISABLED base:0x75,width:1,bytemask:0x1
-		BITS width:1,mask:0x1
-	IO_INAT2_FORCE_DISABLED base:0x76,width:1,bytemask:0x1
-		BITS width:1,mask:0x1
-	IO_INBT2_FORCE_DISABLED base:0x77,width:1,bytemask:0x1
-		BITS width:1,mask:0x1
-	IO_INAT3_FORCE_DISABLED base:0x78,width:1,bytemask:0x1
-		BITS width:1,mask:0x1
-	IO_INBT3_FORCE_DISABLED base:0x79,width:1,bytemask:0x1
-		BITS width:1,mask:0x1
-	IO_ODATAT1_FORCE_DISABLED base:0x7a,width:1,bytemask:0x1
-		BITS width:1,mask:0x1
-	IO_ODATAT2_FORCE_DISABLED base:0x7b,width:1,bytemask:0x1
-		BITS width:1,mask:0x1
-	IO_ODATAT3_FORCE_DISABLED base:0x7c,width:1,bytemask:0x1
-		BITS width:1,mask:0x1
-	RUN_CYCLE_COUNT base:0x7d,width:48,bytemask:0x3f
-		BITS width:48,mask:0xffffffff
-	CURRENT_RUN_CYCLE_COUNT base:0x83,width:48,bytemask:0x3f
-		BITS width:48,mask:0xffffffff
-	DBG_CTLD_ALMOST_EMPTY base:0x89,width:6,bytemask:0x1
-		BITS width:6,mask:0x3f
-	DBG_CTLD_DONE base:0x8a,width:6,bytemask:0x1
-		BITS width:6,mask:0x3f
-	DBG_CTLD_EMPTY base:0x8b,width:6,bytemask:0x1
-		BITS width:6,mask:0x3f
-	DBG_CTLD_READ base:0x8c,width:6,bytemask:0x1
-		BITS width:6,mask:0x3f
-	DBG_CTLD_READ_PIPE_DBG base:0x8d,width:18,bytemask:0x7
-		BITS width:18,mask:0x3ffff
-	DBG_CTLD_REQUEST base:0x90,width:6,bytemask:0x1
-		BITS width:6,mask:0x3f
-	DBG_DONE_OUT base:0x91,width:1,bytemask:0x1
-		BITS width:1,mask:0x1
-	DBG_FILL_LEVEL base:0x92,width:4,bytemask:0x1
-		BITS width:4,mask:0xf
-	DBG_FLUSH_LEVEL base:0x93,width:4,bytemask:0x1
-		BITS width:4,mask:0xf
-	DBG_FLUSH_START base:0x94,width:1,bytemask:0x1
-		BITS width:1,mask:0x1
-	DBG_FLUSH_START_LEVEL base:0x95,width:4,bytemask:0x1
-		BITS width:4,mask:0xf
-	DBG_FLUSHING base:0x96,width:1,bytemask:0x1
-		BITS width:1,mask:0x1
-	DBG_FULL_LEVEL base:0x97,width:4,bytemask:0x1
-		BITS width:4,mask:0xf
-	DBG_OUT_STALL base:0x98,width:3,bytemask:0x1
-		BITS width:3,mask:0x7
-	DBG_OUT_VALID base:0x99,width:3,bytemask:0x1
-		BITS width:3,mask:0x7
-	DBG_STALL_VECTOR base:0x9a,width:3,bytemask:0x1
-		BITS width:3,mask:0x7
-IFPGA version:1,000,instance:0
-	IFPGA_CTRL base:0x9b,width:8,bytemask:0x1
-		BITS width:8,mask:0xff
-SIGNALFORWARDINGADAPTER version:1,000,instance:0
-	SFA_FORWARD_EN base:0x9c,width:32,bytemask:0xf
-		BITS width:32,mask:0xffffffff

tests/StreamFMA_MAX5C_DFE_SIM/scratch/manager_clock_report.txt

@@ -1,87 +0,0 @@
-Clock: STREAM (frequency 100.0 MHz phase 0.0 duty cycle 0.5 static)
-	[STREAM] addrgen_cmd_MemoryControllerPro0_oDataT2 (ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_oDataT2)
-	[STREAM] addrgen_cmd_MemoryControllerPro0_oDataT1 (ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_oDataT1)
-	[STREAM] addrgen_cmd_MemoryControllerPro0_inBT2 (ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_inBT2)
-	[STREAM] addrgen_cmd_MemoryControllerPro0_inAT3 (ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_inAT3)
-	[STREAM] addrgen_cmd_MemoryControllerPro0_inBT3 (ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_inBT3)
-	[STREAM] addrgen_cmd_MemoryControllerPro0_inAT2 (ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_inAT2)
-	[STREAM] Stream_58 (Fifo)
-	[STREAM] Stream_50 (Fifo)
-	[STREAM] Stream_42 (Fifo)
-	[STREAM] Stream_62 (Fifo)
-	[STREAM] Stream_54 (Fifo)
-	[STREAM] Stream_46 (Fifo)
-	[STREAM] Stream_104 (Fifo)
-	[STREAM] Stream_100 (Fifo)
-	[STREAM] Stream_96 (StreamPullPushAdapter)
-	[STREAM] Stream_90 (Fifo)
-	[STREAM] Stream_90 (Fifo)
-	[STREAM] Stream_60 (DualAspectReg)
-	[STREAM] Stream_92 (StreamPullPushAdapter)
-	[STREAM] Stream_8 (DualAspectMux)
-	[STREAM] Stream_108 (Fifo)
-	[STREAM] Stream_108 (Fifo)
-	[STREAM] Stream_112 (Fifo)
-	[STREAM] Stream_112 (Fifo)
-	[STREAM] Stream_10 (DualAspectMux)
-	[STREAM] MemoryControllerPro0 (ManagerStateMachine_MemoryControllerPro0)
-	[STREAM] MemoryControllerPro0 (ManagerStateMachine_MemoryControllerPro0)
-	[STREAM] Stream_12 (DualAspectMux)
-	[STREAM] Stream_14 (DualAspectMux)
-	[STREAM] Stream_116 (Fifo)
-	[STREAM] Stream_116 (Fifo)
-	[STREAM] Stream_120 (Fifo)
-	[STREAM] Stream_120 (Fifo)
-	[STREAM] StreamFMAKernel (Kernel)
-	[STREAM] Stream_122 (Fifo)
-	[STREAM] Stream_94 (Fifo)
-	[STREAM] Stream_94 (Fifo)
-	[STREAM] Stream_64 (DualAspectReg)
-Clock: DDR_CLK_a (frequency 266.6 MHz phase 0.0 duty cycle 0.5 static)
-	[DDR_CLK_a] Stream_84 (Fifo)
-	[DDR_CLK_a] MemoryControllerInterface_a (MemoryControllerInterface_a)
-	[DDR_CLK_a] Stream_34_pipeline_4 (Stream_34_pipeline)
-	[DDR_CLK_a] Stream_68 (Fifo)
-Clock: DDR_CLK_b (frequency 266.6 MHz phase 0.0 duty cycle 0.5 static)
-	[DDR_CLK_b] Stream_80 (Fifo)
-	[DDR_CLK_b] MemoryControllerInterface_b (MemoryControllerInterface_b)
-	[DDR_CLK_b] Stream_29_pipeline_4 (Stream_29_pipeline)
-	[DDR_CLK_b] Stream_72 (Fifo)
-Clock: PCIE (frequency 125.0 MHz phase 0.0 duty cycle 0.5 static)
-	[PCIE] inAT1 (PCIe_From_Host)
-	[PCIE] inBT1 (PCIe_From_Host)
-	[PCIE] Stream_98 (Fifo)
-	[PCIE] Stream_98 (Fifo)
-	[PCIE] Stream_102 (Fifo)
-	[PCIE] Stream_102 (Fifo)
-	[PCIE] Stream_4 (DualAspectMux)
-	[PCIE] Stream_1 (DualAspectMux)
-	[PCIE] Stream_104 (Fifo)
-	[PCIE] Stream_100 (Fifo)
-	[PCIE] Stream_124 (StreamPullPushAdapter)
-	[PCIE] oDataT3 (PCIe_To_Host)
-	[PCIE] Stream_122 (Fifo)
-	[PCIE] Stream_20 (DualAspectReg)
-Clock: MemoryControllerPro0_clk (frequency 272.5 MHz phase 0.0 duty cycle 0.5 static)
-	[MemoryControllerPro0_clk] Stream_58 (Fifo)
-	[MemoryControllerPro0_clk] Stream_50 (Fifo)
-	[MemoryControllerPro0_clk] Stream_42 (Fifo)
-	[MemoryControllerPro0_clk] Stream_62 (Fifo)
-	[MemoryControllerPro0_clk] Stream_54 (Fifo)
-	[MemoryControllerPro0_clk] Stream_46 (Fifo)
-	[MemoryControllerPro0_clk] Stream_28_pipeline_4 (Stream_28_pipeline)
-	[MemoryControllerPro0_clk] Stream_80 (Fifo)
-	[MemoryControllerPro0_clk] Stream_72 (Fifo)
-	[MemoryControllerPro0_clk] Stream_84 (Fifo)
-	[MemoryControllerPro0_clk] Stream_68 (Fifo)
-	[MemoryControllerPro0_clk] Stream_76 (Fifo)
-	[MemoryControllerPro0_clk] MemoryControllerPro0 (ManagerStateMachine_MemoryControllerPro0)
-	[MemoryControllerPro0_clk] MemoryControllerPro0_IntSource (MemoryInterruptSource)
-	[MemoryControllerPro0_clk] Stream_38_pipeline_4 (Stream_38_pipeline)
-	[MemoryControllerPro0_clk] Stream_33_pipeline_4 (Stream_33_pipeline)
-	[MemoryControllerPro0_clk] Stream_88 (Fifo)
-Clock: DDR_CLK_c (frequency 266.6 MHz phase 0.0 duty cycle 0.5 static)
-	[DDR_CLK_c] Stream_39_pipeline_4 (Stream_39_pipeline)
-	[DDR_CLK_c] Stream_76 (Fifo)
-	[DDR_CLK_c] Stream_88 (Fifo)
-	[DDR_CLK_c] MemoryControllerInterface_c (MemoryControllerInterface_c)

tests/StreamFMA_MAX5C_DFE_SIM/scratch/software-sim/build/Makefile.local_rules

@@ -1,23 +0,0 @@
-CXXFLAGS_OPTIONAL := -DHAVE_KERNELS -DMAXFILE_INC="../../MaxCompilerDesignData.dat" -g0  -DSLIC_NO_DECLARATIONS 
-CFLAGS_OPTIONAL   := -DMAXFILE_INC="../../MaxCompilerDesignData.dat" -g0  -DSLIC_NO_DECLARATIONS 
-LDFLAGS_OPTIONAL  := -O2 -s
-TARGET_BIN := StreamFMA.so
-MODE := SHARED_OBJECT
-OBJS :=  \
-	$(OBJDIR)/StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_oDataT2.o \
-	$(OBJDIR)/StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_oDataT2.o \
-	$(OBJDIR)/StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_oDataT1.o \
-	$(OBJDIR)/StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_oDataT1.o \
-	$(OBJDIR)/StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_inBT2.o \
-	$(OBJDIR)/StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_inBT2.o \
-	$(OBJDIR)/StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_inAT3.o \
-	$(OBJDIR)/StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_inAT3.o \
-	$(OBJDIR)/StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_inBT3.o \
-	$(OBJDIR)/StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_inBT3.o \
-	$(OBJDIR)/StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_inAT2.o \
-	$(OBJDIR)/StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_inAT2.o \
-	$(OBJDIR)/StateMachineManagerBlock_impl_MemoryControllerPro0.o \
-	$(OBJDIR)/StateMachine_impl_M_MemoryControllerPro0.o \
-	$(OBJDIR)/StreamFMAKernel_exec0.O2.o \
-	$(OBJDIR)/StreamFMAKernel.O0.o \
-	$(OBJDIR)/StreamFMAKernel_Templates.O2.o

tests/StreamFMA_MAX5C_DFE_SIM/scratch/software-sim/build/Makefile.local_rules.tmp

@@ -1,23 +0,0 @@
-CXXFLAGS_OPTIONAL := -DHAVE_KERNELS -DMAXFILE_INC="../../MaxCompilerDesignData.dat" -g0  -DSLIC_NO_DECLARATIONS 
-CFLAGS_OPTIONAL   := -DMAXFILE_INC="../../MaxCompilerDesignData.dat" -g0  -DSLIC_NO_DECLARATIONS 
-LDFLAGS_OPTIONAL  := -O2 -s
-TARGET_BIN := StreamFMA.so
-MODE := SHARED_OBJECT
-OBJS :=  \
-	$(OBJDIR)/StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_oDataT2.o \
-	$(OBJDIR)/StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_oDataT2.o \
-	$(OBJDIR)/StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_oDataT1.o \
-	$(OBJDIR)/StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_oDataT1.o \
-	$(OBJDIR)/StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_inBT2.o \
-	$(OBJDIR)/StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_inBT2.o \
-	$(OBJDIR)/StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_inAT3.o \
-	$(OBJDIR)/StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_inAT3.o \
-	$(OBJDIR)/StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_inBT3.o \
-	$(OBJDIR)/StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_inBT3.o \
-	$(OBJDIR)/StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_inAT2.o \
-	$(OBJDIR)/StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_inAT2.o \
-	$(OBJDIR)/StateMachineManagerBlock_impl_MemoryControllerPro0.o \
-	$(OBJDIR)/StateMachine_impl_M_MemoryControllerPro0.o \
-	$(OBJDIR)/StreamFMAKernel_exec0.O2.o \
-	$(OBJDIR)/StreamFMAKernel.O0.o \
-	$(OBJDIR)/StreamFMAKernel_Templates.O2.o

tests/StreamFMA_MAX5C_DFE_SIM/scratch/software-sim/build/StateMachineManagerBlock_impl_MemoryControllerPro0.cpp

@@ -1,300 +0,0 @@
-#include "StateMachineManagerBlock_impl_MemoryControllerPro0.h"
-
-namespace maxcompilersim {
-namespace state_machine {
-
-ManagerBlockSM_MemoryControllerPro0::ManagerBlockSM_MemoryControllerPro0(const std::string &name)
-	: ManagerBlockSync(name)
-	, Debuggable(this, name)
-	, m_sm(getDebugStreams(), 0)
-	, m_input_read_stream_maxj_b(registerPullInput("read_stream_maxj_b"), 512)
-	, m_input_read_stream_maxj_a(registerPullInput("read_stream_maxj_a"), 512)
-	, m_input_read_stream_maxj_c(registerPullInput("read_stream_maxj_c"), 512)
-	, m_output_read_0(registerPullOutput("read_0"), 1536)
-	, m_output_read_2(registerPullOutput("read_2"), 1536)
-	, m_output_read_1(registerPullOutput("read_1"), 1536)
-	, m_output_read_3(registerPullOutput("read_3"), 1536)
-	, m_input_read_command_3(registerPushInput("read_command_3"), 64, 8)
-	, m_input_read_command_2(registerPushInput("read_command_2"), 64, 8)
-	, m_input_read_command_1(registerPushInput("read_command_1"), 64, 8)
-	, m_input_read_command_0(registerPushInput("read_command_0"), 64, 8)
-	, m_input_write_command_1(registerPushInput("write_command_1"), 64, 8)
-	, m_input_write_command_0(registerPushInput("write_command_0"), 64, 8)
-	, m_input_write_1(registerPushInput("write_1"), 1536, 8)
-	, m_input_write_0(registerPushInput("write_0"), 1536, 8)
-	, m_output_Tag_Out(registerPushOutput("Tag_Out"), 1, 1)
-	, m_output_cmd_stream_maxj_b(registerPushOutput("cmd_stream_maxj_b"), 544, 3)
-	, m_output_cmd_stream_maxj_a(registerPushOutput("cmd_stream_maxj_a"), 544, 3)
-	, m_output_cmd_stream_maxj_c(registerPushOutput("cmd_stream_maxj_c"), 544, 3)
-{
-	// register scalar inputs
-	registerMappedRegister("Mcp_Int_Disable_OR", Data(6));
-	registerMappedRegister("Mcp_Int_Enable_AND", Data(6));
-
-}
-
-void ManagerBlockSM_MemoryControllerPro0::reset() {
-	m_sm.reset();
-
-	// update scalar inputs
-	m_sm.inputdata_Mcp_Int_Disable_OR = getMappedRegValue<6>("Mcp_Int_Disable_OR");
-	m_sm.inputdata_Mcp_Int_Enable_AND = getMappedRegValue<6>("Mcp_Int_Enable_AND");
-
-	// reset pull inputs
-	m_input_read_stream_maxj_b.reset();
-	m_input_read_stream_maxj_a.reset();
-	m_input_read_stream_maxj_c.reset();
-
-	// reset pull outputs
-	m_output_read_0.reset();
-	m_output_read_2.reset();
-	m_output_read_1.reset();
-	m_output_read_3.reset();
-
-	// reset push inputs
-	m_input_read_command_3.reset();
-	m_input_read_command_2.reset();
-	m_input_read_command_1.reset();
-	m_input_read_command_0.reset();
-	m_input_write_command_1.reset();
-	m_input_write_command_0.reset();
-	m_input_write_1.reset();
-	m_input_write_0.reset();
-
-	// reset push outputs
-	m_output_Tag_Out.reset();
-	m_output_cmd_stream_maxj_b.reset();
-	m_output_cmd_stream_maxj_a.reset();
-	m_output_cmd_stream_maxj_c.reset();
-}
-
-bool ManagerBlockSM_MemoryControllerPro0::runCycle() {
-	// pass through 'pull' signals and data to state machine
-	if (m_input_read_stream_maxj_b.read)
-		m_input_read_stream_maxj_b.clearData();
-
-	m_sm.inputdata_read_stream_maxj_b  = m_input_read_stream_maxj_b.getData().toVarIntU<512>();
-	m_sm.inputempty_read_stream_maxj_b = varint_u<1>(m_input_read_stream_maxj_b.signalEmpty());
-	// FIXME Almost empty is not simulated. It is always high.
-	m_sm.inputalmost_empty_read_stream_maxj_b = varint_u<1>(1);
-	if (m_input_read_stream_maxj_a.read)
-		m_input_read_stream_maxj_a.clearData();
-
-	m_sm.inputdata_read_stream_maxj_a  = m_input_read_stream_maxj_a.getData().toVarIntU<512>();
-	m_sm.inputempty_read_stream_maxj_a = varint_u<1>(m_input_read_stream_maxj_a.signalEmpty());
-	// FIXME Almost empty is not simulated. It is always high.
-	m_sm.inputalmost_empty_read_stream_maxj_a = varint_u<1>(1);
-	if (m_input_read_stream_maxj_c.read)
-		m_input_read_stream_maxj_c.clearData();
-
-	m_sm.inputdata_read_stream_maxj_c  = m_input_read_stream_maxj_c.getData().toVarIntU<512>();
-	m_sm.inputempty_read_stream_maxj_c = varint_u<1>(m_input_read_stream_maxj_c.signalEmpty());
-	// FIXME Almost empty is not simulated. It is always high.
-	m_sm.inputalmost_empty_read_stream_maxj_c = varint_u<1>(1);
-
-	// get data for 'pull' inputs for the next cycle
-	if (m_input_read_stream_maxj_b.signalEmpty() && !isPullInputEmpty(m_input_read_stream_maxj_b.port))
-		m_input_read_stream_maxj_b.setData(pullInput(m_input_read_stream_maxj_b.port));
-	if (m_input_read_stream_maxj_a.signalEmpty() && !isPullInputEmpty(m_input_read_stream_maxj_a.port))
-		m_input_read_stream_maxj_a.setData(pullInput(m_input_read_stream_maxj_a.port));
-	if (m_input_read_stream_maxj_c.signalEmpty() && !isPullInputEmpty(m_input_read_stream_maxj_c.port))
-		m_input_read_stream_maxj_c.setData(pullInput(m_input_read_stream_maxj_c.port));
-
-	// push inputs: pass through signals and data
-	m_sm.inputvalid_read_command_3 = varint_u<1>(m_input_read_command_3.valid());
-	if (m_sm.inputvalid_read_command_3)
-		m_sm.inputdata_read_command_3 = m_input_read_command_3.getData().toVarIntU<64>();
-	m_sm.inputvalid_read_command_2 = varint_u<1>(m_input_read_command_2.valid());
-	if (m_sm.inputvalid_read_command_2)
-		m_sm.inputdata_read_command_2 = m_input_read_command_2.getData().toVarIntU<64>();
-	m_sm.inputvalid_read_command_1 = varint_u<1>(m_input_read_command_1.valid());
-	if (m_sm.inputvalid_read_command_1)
-		m_sm.inputdata_read_command_1 = m_input_read_command_1.getData().toVarIntU<64>();
-	m_sm.inputvalid_read_command_0 = varint_u<1>(m_input_read_command_0.valid());
-	if (m_sm.inputvalid_read_command_0)
-		m_sm.inputdata_read_command_0 = m_input_read_command_0.getData().toVarIntU<64>();
-	m_sm.inputvalid_write_command_1 = varint_u<1>(m_input_write_command_1.valid());
-	if (m_sm.inputvalid_write_command_1)
-		m_sm.inputdata_write_command_1 = m_input_write_command_1.getData().toVarIntU<64>();
-	m_sm.inputvalid_write_command_0 = varint_u<1>(m_input_write_command_0.valid());
-	if (m_sm.inputvalid_write_command_0)
-		m_sm.inputdata_write_command_0 = m_input_write_command_0.getData().toVarIntU<64>();
-	m_sm.inputvalid_write_1 = varint_u<1>(m_input_write_1.valid());
-	if (m_sm.inputvalid_write_1)
-		m_sm.inputdata_write_1 = m_input_write_1.getData().toVarIntU<1536>();
-	m_sm.inputvalid_write_0 = varint_u<1>(m_input_write_0.valid());
-	if (m_sm.inputvalid_write_0)
-		m_sm.inputdata_write_0 = m_input_write_0.getData().toVarIntU<1536>();
-
-	// pass through 'pull' output control signals
-	m_sm.outputread_read_0 = m_output_read_0.read;
-	m_sm.outputread_read_2 = m_output_read_2.read;
-	m_sm.outputread_read_1 = m_output_read_1.read;
-	m_sm.outputread_read_3 = m_output_read_3.read;
-
-	// push outputs - pass through stall signal
-	m_sm.outputstall_Tag_Out = varint_u<1>(m_output_Tag_Out.stalled());
-	m_sm.outputstall_cmd_stream_maxj_b = varint_u<1>(m_output_cmd_stream_maxj_b.stalled());
-	m_sm.outputstall_cmd_stream_maxj_a = varint_u<1>(m_output_cmd_stream_maxj_a.stalled());
-	m_sm.outputstall_cmd_stream_maxj_c = varint_u<1>(m_output_cmd_stream_maxj_c.stalled());
-
-	// update scalar inputs
-	m_sm.inputdata_Mcp_Int_Disable_OR = getMappedRegValue<6>("Mcp_Int_Disable_OR");
-	m_sm.inputdata_Mcp_Int_Enable_AND = getMappedRegValue<6>("Mcp_Int_Enable_AND");
-
-	// run the state machine
-	m_sm.execute();
-
-	// update inputs/outputs/signals..
-	// get 'pull' input control signals
-	m_input_read_stream_maxj_b.read = m_sm.inputread_read_stream_maxj_b;
-	m_input_read_stream_maxj_a.read = m_sm.inputread_read_stream_maxj_a;
-	m_input_read_stream_maxj_c.read = m_sm.inputread_read_stream_maxj_c;
-
-	// update push inputs (remove current data and update stall signal)
-	m_input_read_command_3.clearData();
-	m_input_read_command_3.sm_stalled = m_sm.inputstall_read_command_3;
-	m_input_read_command_2.clearData();
-	m_input_read_command_2.sm_stalled = m_sm.inputstall_read_command_2;
-	m_input_read_command_1.clearData();
-	m_input_read_command_1.sm_stalled = m_sm.inputstall_read_command_1;
-	m_input_read_command_0.clearData();
-	m_input_read_command_0.sm_stalled = m_sm.inputstall_read_command_0;
-	m_input_write_command_1.clearData();
-	m_input_write_command_1.sm_stalled = m_sm.inputstall_write_command_1;
-	m_input_write_command_0.clearData();
-	m_input_write_command_0.sm_stalled = m_sm.inputstall_write_command_0;
-	m_input_write_1.clearData();
-	m_input_write_1.sm_stalled = m_sm.inputstall_write_1;
-	m_input_write_0.clearData();
-	m_input_write_0.sm_stalled = m_sm.inputstall_write_0;
-
-	// get 'pull' output data & control signals
-	// (1) update read signal in case we had a read/empty conflict
-	m_output_read_0.read = m_sm.outputread_read_0;
-
-	// (2) see if we need to grab output data
-	if (m_output_read_0.hadReadInLastCycle()) {
-		m_output_read_0.setData(varint_u<1536>(m_sm.outputdata_read_0));
-	}
-	// (3) determine read for the next cycle (we can only read every other cycle..)
-	m_output_read_0.newCycle(!m_output_read_0.haveData() && !m_output_read_0.read && !m_sm.outputempty_read_0);
-	// (1) update read signal in case we had a read/empty conflict
-	m_output_read_2.read = m_sm.outputread_read_2;
-
-	// (2) see if we need to grab output data
-	if (m_output_read_2.hadReadInLastCycle()) {
-		m_output_read_2.setData(varint_u<1536>(m_sm.outputdata_read_2));
-	}
-	// (3) determine read for the next cycle (we can only read every other cycle..)
-	m_output_read_2.newCycle(!m_output_read_2.haveData() && !m_output_read_2.read && !m_sm.outputempty_read_2);
-	// (1) update read signal in case we had a read/empty conflict
-	m_output_read_1.read = m_sm.outputread_read_1;
-
-	// (2) see if we need to grab output data
-	if (m_output_read_1.hadReadInLastCycle()) {
-		m_output_read_1.setData(varint_u<1536>(m_sm.outputdata_read_1));
-	}
-	// (3) determine read for the next cycle (we can only read every other cycle..)
-	m_output_read_1.newCycle(!m_output_read_1.haveData() && !m_output_read_1.read && !m_sm.outputempty_read_1);
-	// (1) update read signal in case we had a read/empty conflict
-	m_output_read_3.read = m_sm.outputread_read_3;
-
-	// (2) see if we need to grab output data
-	if (m_output_read_3.hadReadInLastCycle()) {
-		m_output_read_3.setData(varint_u<1536>(m_sm.outputdata_read_3));
-	}
-	// (3) determine read for the next cycle (we can only read every other cycle..)
-	m_output_read_3.newCycle(!m_output_read_3.haveData() && !m_output_read_3.read && !m_sm.outputempty_read_3);
-
-	// update push outputs
-	m_output_Tag_Out.valid = m_sm.outputvalid_Tag_Out;
-	try {
-		if (m_output_Tag_Out.valid)
-			m_output_Tag_Out.push_back(varint_u<1>(m_sm.outputdata_Tag_Out));
-	} catch (SimException) {
-		throw SimException("Push output 'Tag_Out' in state machine 'Manager_MemoryControllerPro0' is full");
-	}
-	m_output_Tag_Out.setOutputStalled(isPushOutputStalled(m_output_Tag_Out.port));
-	if (m_output_Tag_Out.haveData() && !isPushOutputStalled(m_output_Tag_Out.port)) {
-		pushOutput(m_output_Tag_Out.port, m_output_Tag_Out.peek());
-		m_output_Tag_Out.pop_front();
-	}
-	m_output_cmd_stream_maxj_b.valid = m_sm.outputvalid_cmd_stream_maxj_b;
-	try {
-		if (m_output_cmd_stream_maxj_b.valid)
-			m_output_cmd_stream_maxj_b.push_back(varint_u<544>(m_sm.outputdata_cmd_stream_maxj_b));
-	} catch (SimException) {
-		throw SimException("Push output 'cmd_stream_maxj_b' in state machine 'Manager_MemoryControllerPro0' is full");
-	}
-	m_output_cmd_stream_maxj_b.setOutputStalled(isPushOutputStalled(m_output_cmd_stream_maxj_b.port));
-	if (m_output_cmd_stream_maxj_b.haveData() && !isPushOutputStalled(m_output_cmd_stream_maxj_b.port)) {
-		pushOutput(m_output_cmd_stream_maxj_b.port, m_output_cmd_stream_maxj_b.peek());
-		m_output_cmd_stream_maxj_b.pop_front();
-	}
-	m_output_cmd_stream_maxj_a.valid = m_sm.outputvalid_cmd_stream_maxj_a;
-	try {
-		if (m_output_cmd_stream_maxj_a.valid)
-			m_output_cmd_stream_maxj_a.push_back(varint_u<544>(m_sm.outputdata_cmd_stream_maxj_a));
-	} catch (SimException) {
-		throw SimException("Push output 'cmd_stream_maxj_a' in state machine 'Manager_MemoryControllerPro0' is full");
-	}
-	m_output_cmd_stream_maxj_a.setOutputStalled(isPushOutputStalled(m_output_cmd_stream_maxj_a.port));
-	if (m_output_cmd_stream_maxj_a.haveData() && !isPushOutputStalled(m_output_cmd_stream_maxj_a.port)) {
-		pushOutput(m_output_cmd_stream_maxj_a.port, m_output_cmd_stream_maxj_a.peek());
-		m_output_cmd_stream_maxj_a.pop_front();
-	}
-	m_output_cmd_stream_maxj_c.valid = m_sm.outputvalid_cmd_stream_maxj_c;
-	try {
-		if (m_output_cmd_stream_maxj_c.valid)
-			m_output_cmd_stream_maxj_c.push_back(varint_u<544>(m_sm.outputdata_cmd_stream_maxj_c));
-	} catch (SimException) {
-		throw SimException("Push output 'cmd_stream_maxj_c' in state machine 'Manager_MemoryControllerPro0' is full");
-	}
-	m_output_cmd_stream_maxj_c.setOutputStalled(isPushOutputStalled(m_output_cmd_stream_maxj_c.port));
-	if (m_output_cmd_stream_maxj_c.haveData() && !isPushOutputStalled(m_output_cmd_stream_maxj_c.port)) {
-		pushOutput(m_output_cmd_stream_maxj_c.port, m_output_cmd_stream_maxj_c.peek());
-		m_output_cmd_stream_maxj_c.pop_front();
-	}
-
-
-	getDebugStreams()->finishCycle();
-	return true;
-}
-
-const PullOutput &ManagerBlockSM_MemoryControllerPro0::getPullOutput(const t_port_number port) const {
-	if (port == m_output_read_0.port)
-		return m_output_read_0;
-	if (port == m_output_read_2.port)
-		return m_output_read_2;
-	if (port == m_output_read_1.port)
-		return m_output_read_1;
-	if (port == m_output_read_3.port)
-		return m_output_read_3;
-
-	throw std::runtime_error("Invalid output port number.");
-}
-
-const PushInput &ManagerBlockSM_MemoryControllerPro0::getPushInput(const t_port_number port) const {
-	if (port == m_input_read_command_3.port)
-		return m_input_read_command_3;
-	if (port == m_input_read_command_2.port)
-		return m_input_read_command_2;
-	if (port == m_input_read_command_1.port)
-		return m_input_read_command_1;
-	if (port == m_input_read_command_0.port)
-		return m_input_read_command_0;
-	if (port == m_input_write_command_1.port)
-		return m_input_write_command_1;
-	if (port == m_input_write_command_0.port)
-		return m_input_write_command_0;
-	if (port == m_input_write_1.port)
-		return m_input_write_1;
-	if (port == m_input_write_0.port)
-		return m_input_write_0;
-
-	throw std::runtime_error("Invalid input port number.");
-}
-
-}}
-

tests/StreamFMA_MAX5C_DFE_SIM/scratch/software-sim/build/StateMachineManagerBlock_impl_MemoryControllerPro0.h

@@ -1,119 +0,0 @@
-#pragma once
-
-#include <string>
-
-#include "ManagerSync.h"
-#include "Debuggable.h"
-#include "SimException.h"
-#include "Connections.h"
-#include "MappedElementInterface.h"
-#include "ManagerStateMachine_IO.h"
-#include "PullSync.h"
-#include "PushSync.h"
-#include <deque>
-
-#include "StateMachine_impl_M_MemoryControllerPro0.h"
-
-namespace maxcompilersim {
-namespace state_machine {
-
-class ManagerBlockSM_MemoryControllerPro0
-	: public Debuggable, public MappedElementInterface
-	, public PullSinkSync
-	, public PullSourceSync
-	, public PushSinkSync
-	, public PushSourceSync
-{
-public:
-	ManagerBlockSM_MemoryControllerPro0(const std::string &name);
-	
-	virtual bool runCycle();
-	virtual void reset();
-	
-	// PushSink overrides
-	virtual bool isPushInputStalled(t_port_number input_port) const {
-		return getPushInput(input_port).isStalled();
-	}
-	
-	virtual void pushInput(t_port_number input_port, const maxcompilersim::Data& data) {
-		getPushInput(input_port).pushInput(data);
-	}
-	// PullSource overrides
-	virtual bool isPullOutputEmpty(const t_port_number output_port) const {
-		return !getPullOutput(output_port).haveData();
-	}
-
-protected:
-	// PullSource overrides
-	virtual const Data &peekOutput(const t_port_number output_port) const { return getPullOutput(output_port).peek(); }
-	virtual void pullOutput(const t_port_number output_port) { getPullOutput(output_port).pullAndClearData(); }
-
-private:
-	Manager_MemoryControllerPro0 m_sm;
-
-	template<uint dataWidth>
-	varint_u<dataWidth> getMappedRegValue(const char *name) {
-		MappedRegisterPtr reg(getMappedReg(name));
-		return varint_u<dataWidth>(reg->getData());
-	}
-
-
-	PullInput m_input_read_stream_maxj_b;
-	PullInput m_input_read_stream_maxj_a;
-	PullInput m_input_read_stream_maxj_c;
-
-	const PullOutput &getPullOutput(const t_port_number port) const;
-
-	PullOutput &getPullOutput(const t_port_number port) {
-		return const_cast<PullOutput&>(static_cast<const ManagerBlockSM_MemoryControllerPro0&>(*this).getPullOutput(port));
-	}
-
-	PullOutput m_output_read_0;
-	PullOutput m_output_read_2;
-	PullOutput m_output_read_1;
-	PullOutput m_output_read_3;
-
-	const PushInput &getPushInput(const t_port_number port) const;
-
-	PushInput &getPushInput(const t_port_number port) {
-		return const_cast<PushInput&>(static_cast<const ManagerBlockSM_MemoryControllerPro0&>(*this).getPushInput(port));
-	}
-
-	PushInput m_input_read_command_3;
-	PushInput m_input_read_command_2;
-	PushInput m_input_read_command_1;
-	PushInput m_input_read_command_0;
-	PushInput m_input_write_command_1;
-	PushInput m_input_write_command_0;
-	PushInput m_input_write_1;
-	PushInput m_input_write_0;
-
-	PushOutput m_output_Tag_Out;
-	PushOutput m_output_cmd_stream_maxj_b;
-	PushOutput m_output_cmd_stream_maxj_a;
-	PushOutput m_output_cmd_stream_maxj_c;
-	
-	// Java Sim accessing methods
-	Data getMappedMemValue(const std::string &name, const uint width, const uint entry) {
-		AbstractMappedMemoryPtr mem(getMappedMem(name));
-		return mem->getData(entry);
-	}
-	
-	void setMappedMemValue(const std::string &name, const uint entry, const Data &data) {
-		AbstractMappedMemoryPtr mem(getMappedMem(name));
-		mem->setData(entry, data);
-	}
-
-	Data getMappedRegValue(const std::string &name, const uint width) {
-		MappedRegisterPtr reg(getMappedReg(name));
-		return reg->getData();
-	}
-
-	void setMappedRegValue(const std::string &name, const Data &data) {
-		MappedRegisterPtr reg(getMappedReg(name));
-		reg->setData(data);
-	}
-};
-
-}}
-

tests/StreamFMA_MAX5C_DFE_SIM/scratch/software-sim/build/StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_inAT2.cpp

@@ -1,84 +0,0 @@
-#include "StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_inAT2.h"
-
-namespace maxcompilersim {
-namespace state_machine {
-
-ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_inAT2::ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_inAT2(const std::string &name)
-	: ManagerBlockSync(name)
-	, Debuggable(this, name)
-	, m_sm(getDebugStreams(), 0)
-	, m_output_cgen_out_0(registerPushOutput("cgen_out_0"), 64, 1)
-{
-	// register scalar inputs
-	registerMappedRegister("AGen_Start_X_Addr", Data(32));
-	registerMappedRegister("AGen_Offset_0", Data(31));
-	registerMappedRegister("AGen_CmdSize", Data(8));
-	registerMappedRegister("AGen_Wrap_X", Data(32));
-	registerMappedRegister("AGen_BlockSize_X", Data(33));
-	registerMappedRegister("AGen_Addr_En", Data(1));
-
-}
-
-void ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_inAT2::reset() {
-	m_sm.reset();
-
-	// update scalar inputs
-	m_sm.inputdata_AGen_Start_X_Addr = getMappedRegValue<32>("AGen_Start_X_Addr");
-	m_sm.inputdata_AGen_Offset_0 = getMappedRegValue<31>("AGen_Offset_0");
-	m_sm.inputdata_AGen_CmdSize = getMappedRegValue<8>("AGen_CmdSize");
-	m_sm.inputdata_AGen_Wrap_X = getMappedRegValue<32>("AGen_Wrap_X");
-	m_sm.inputdata_AGen_BlockSize_X = getMappedRegValue<33>("AGen_BlockSize_X");
-	m_sm.inputdata_AGen_Addr_En = getMappedRegValue<1>("AGen_Addr_En");
-
-
-
-
-	// reset push outputs
-	m_output_cgen_out_0.reset();
-}
-
-bool ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_inAT2::runCycle() {
-
-
-
-	// push outputs - pass through stall signal
-	m_sm.outputstall_cgen_out_0 = varint_u<1>(m_output_cgen_out_0.stalled());
-
-	// update scalar inputs
-	m_sm.inputdata_AGen_Start_X_Addr = getMappedRegValue<32>("AGen_Start_X_Addr");
-	m_sm.inputdata_AGen_Offset_0 = getMappedRegValue<31>("AGen_Offset_0");
-	m_sm.inputdata_AGen_CmdSize = getMappedRegValue<8>("AGen_CmdSize");
-	m_sm.inputdata_AGen_Wrap_X = getMappedRegValue<32>("AGen_Wrap_X");
-	m_sm.inputdata_AGen_BlockSize_X = getMappedRegValue<33>("AGen_BlockSize_X");
-	m_sm.inputdata_AGen_Addr_En = getMappedRegValue<1>("AGen_Addr_En");
-
-	// run the state machine
-	m_sm.execute();
-
-	// update inputs/outputs/signals..
-
-
-
-	// update push outputs
-	m_output_cgen_out_0.valid = m_sm.outputvalid_cgen_out_0;
-	try {
-		if (m_output_cgen_out_0.valid)
-			m_output_cgen_out_0.push_back(varint_u<64>(m_sm.outputdata_cgen_out_0));
-	} catch (SimException) {
-		throw SimException("Push output 'cgen_out_0' in state machine 'Manager_addrgen_cmd_MemoryControllerPro0_inAT2' is full");
-	}
-	m_output_cgen_out_0.setOutputStalled(isPushOutputStalled(m_output_cgen_out_0.port));
-	if (m_output_cgen_out_0.haveData() && !isPushOutputStalled(m_output_cgen_out_0.port)) {
-		pushOutput(m_output_cgen_out_0.port, m_output_cgen_out_0.peek());
-		m_output_cgen_out_0.pop_front();
-	}
-
-
-	getDebugStreams()->finishCycle();
-	return true;
-}
-
-
-
-}}
-

tests/StreamFMA_MAX5C_DFE_SIM/scratch/software-sim/build/StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_inAT2.h

@@ -1,70 +0,0 @@
-#pragma once
-
-#include <string>
-
-#include "ManagerSync.h"
-#include "Debuggable.h"
-#include "SimException.h"
-#include "Connections.h"
-#include "MappedElementInterface.h"
-#include "ManagerStateMachine_IO.h"
-#include "PushSync.h"
-#include <deque>
-
-#include "StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_inAT2.h"
-
-namespace maxcompilersim {
-namespace state_machine {
-
-class ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_inAT2
-	: public Debuggable, public MappedElementInterface
-	, public PushSourceSync
-{
-public:
-	ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_inAT2(const std::string &name);
-	
-	virtual bool runCycle();
-	virtual void reset();
-	
-
-protected:
-
-private:
-	Manager_addrgen_cmd_MemoryControllerPro0_inAT2 m_sm;
-
-	template<uint dataWidth>
-	varint_u<dataWidth> getMappedRegValue(const char *name) {
-		MappedRegisterPtr reg(getMappedReg(name));
-		return varint_u<dataWidth>(reg->getData());
-	}
-
-
-
-
-
-	PushOutput m_output_cgen_out_0;
-	
-	// Java Sim accessing methods
-	Data getMappedMemValue(const std::string &name, const uint width, const uint entry) {
-		AbstractMappedMemoryPtr mem(getMappedMem(name));
-		return mem->getData(entry);
-	}
-	
-	void setMappedMemValue(const std::string &name, const uint entry, const Data &data) {
-		AbstractMappedMemoryPtr mem(getMappedMem(name));
-		mem->setData(entry, data);
-	}
-
-	Data getMappedRegValue(const std::string &name, const uint width) {
-		MappedRegisterPtr reg(getMappedReg(name));
-		return reg->getData();
-	}
-
-	void setMappedRegValue(const std::string &name, const Data &data) {
-		MappedRegisterPtr reg(getMappedReg(name));
-		reg->setData(data);
-	}
-};
-
-}}
-

tests/StreamFMA_MAX5C_DFE_SIM/scratch/software-sim/build/StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_inAT3.cpp

@@ -1,84 +0,0 @@
-#include "StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_inAT3.h"
-
-namespace maxcompilersim {
-namespace state_machine {
-
-ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_inAT3::ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_inAT3(const std::string &name)
-	: ManagerBlockSync(name)
-	, Debuggable(this, name)
-	, m_sm(getDebugStreams(), 0)
-	, m_output_cgen_out_0(registerPushOutput("cgen_out_0"), 64, 1)
-{
-	// register scalar inputs
-	registerMappedRegister("AGen_Start_X_Addr", Data(32));
-	registerMappedRegister("AGen_Offset_0", Data(31));
-	registerMappedRegister("AGen_CmdSize", Data(8));
-	registerMappedRegister("AGen_Wrap_X", Data(32));
-	registerMappedRegister("AGen_BlockSize_X", Data(33));
-	registerMappedRegister("AGen_Addr_En", Data(1));
-
-}
-
-void ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_inAT3::reset() {
-	m_sm.reset();
-
-	// update scalar inputs
-	m_sm.inputdata_AGen_Start_X_Addr = getMappedRegValue<32>("AGen_Start_X_Addr");
-	m_sm.inputdata_AGen_Offset_0 = getMappedRegValue<31>("AGen_Offset_0");
-	m_sm.inputdata_AGen_CmdSize = getMappedRegValue<8>("AGen_CmdSize");
-	m_sm.inputdata_AGen_Wrap_X = getMappedRegValue<32>("AGen_Wrap_X");
-	m_sm.inputdata_AGen_BlockSize_X = getMappedRegValue<33>("AGen_BlockSize_X");
-	m_sm.inputdata_AGen_Addr_En = getMappedRegValue<1>("AGen_Addr_En");
-
-
-
-
-	// reset push outputs
-	m_output_cgen_out_0.reset();
-}
-
-bool ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_inAT3::runCycle() {
-
-
-
-	// push outputs - pass through stall signal
-	m_sm.outputstall_cgen_out_0 = varint_u<1>(m_output_cgen_out_0.stalled());
-
-	// update scalar inputs
-	m_sm.inputdata_AGen_Start_X_Addr = getMappedRegValue<32>("AGen_Start_X_Addr");
-	m_sm.inputdata_AGen_Offset_0 = getMappedRegValue<31>("AGen_Offset_0");
-	m_sm.inputdata_AGen_CmdSize = getMappedRegValue<8>("AGen_CmdSize");
-	m_sm.inputdata_AGen_Wrap_X = getMappedRegValue<32>("AGen_Wrap_X");
-	m_sm.inputdata_AGen_BlockSize_X = getMappedRegValue<33>("AGen_BlockSize_X");
-	m_sm.inputdata_AGen_Addr_En = getMappedRegValue<1>("AGen_Addr_En");
-
-	// run the state machine
-	m_sm.execute();
-
-	// update inputs/outputs/signals..
-
-
-
-	// update push outputs
-	m_output_cgen_out_0.valid = m_sm.outputvalid_cgen_out_0;
-	try {
-		if (m_output_cgen_out_0.valid)
-			m_output_cgen_out_0.push_back(varint_u<64>(m_sm.outputdata_cgen_out_0));
-	} catch (SimException) {
-		throw SimException("Push output 'cgen_out_0' in state machine 'Manager_addrgen_cmd_MemoryControllerPro0_inAT3' is full");
-	}
-	m_output_cgen_out_0.setOutputStalled(isPushOutputStalled(m_output_cgen_out_0.port));
-	if (m_output_cgen_out_0.haveData() && !isPushOutputStalled(m_output_cgen_out_0.port)) {
-		pushOutput(m_output_cgen_out_0.port, m_output_cgen_out_0.peek());
-		m_output_cgen_out_0.pop_front();
-	}
-
-
-	getDebugStreams()->finishCycle();
-	return true;
-}
-
-
-
-}}
-

tests/StreamFMA_MAX5C_DFE_SIM/scratch/software-sim/build/StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_inAT3.h

@@ -1,70 +0,0 @@
-#pragma once
-
-#include <string>
-
-#include "ManagerSync.h"
-#include "Debuggable.h"
-#include "SimException.h"
-#include "Connections.h"
-#include "MappedElementInterface.h"
-#include "ManagerStateMachine_IO.h"
-#include "PushSync.h"
-#include <deque>
-
-#include "StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_inAT3.h"
-
-namespace maxcompilersim {
-namespace state_machine {
-
-class ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_inAT3
-	: public Debuggable, public MappedElementInterface
-	, public PushSourceSync
-{
-public:
-	ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_inAT3(const std::string &name);
-	
-	virtual bool runCycle();
-	virtual void reset();
-	
-
-protected:
-
-private:
-	Manager_addrgen_cmd_MemoryControllerPro0_inAT3 m_sm;
-
-	template<uint dataWidth>
-	varint_u<dataWidth> getMappedRegValue(const char *name) {
-		MappedRegisterPtr reg(getMappedReg(name));
-		return varint_u<dataWidth>(reg->getData());
-	}
-
-
-
-
-
-	PushOutput m_output_cgen_out_0;
-	
-	// Java Sim accessing methods
-	Data getMappedMemValue(const std::string &name, const uint width, const uint entry) {
-		AbstractMappedMemoryPtr mem(getMappedMem(name));
-		return mem->getData(entry);
-	}
-	
-	void setMappedMemValue(const std::string &name, const uint entry, const Data &data) {
-		AbstractMappedMemoryPtr mem(getMappedMem(name));
-		mem->setData(entry, data);
-	}
-
-	Data getMappedRegValue(const std::string &name, const uint width) {
-		MappedRegisterPtr reg(getMappedReg(name));
-		return reg->getData();
-	}
-
-	void setMappedRegValue(const std::string &name, const Data &data) {
-		MappedRegisterPtr reg(getMappedReg(name));
-		reg->setData(data);
-	}
-};
-
-}}
-

tests/StreamFMA_MAX5C_DFE_SIM/scratch/software-sim/build/StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_inBT2.cpp

@@ -1,84 +0,0 @@
-#include "StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_inBT2.h"
-
-namespace maxcompilersim {
-namespace state_machine {
-
-ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_inBT2::ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_inBT2(const std::string &name)
-	: ManagerBlockSync(name)
-	, Debuggable(this, name)
-	, m_sm(getDebugStreams(), 0)
-	, m_output_cgen_out_0(registerPushOutput("cgen_out_0"), 64, 1)
-{
-	// register scalar inputs
-	registerMappedRegister("AGen_Start_X_Addr", Data(32));
-	registerMappedRegister("AGen_Offset_0", Data(31));
-	registerMappedRegister("AGen_CmdSize", Data(8));
-	registerMappedRegister("AGen_Wrap_X", Data(32));
-	registerMappedRegister("AGen_BlockSize_X", Data(33));
-	registerMappedRegister("AGen_Addr_En", Data(1));
-
-}
-
-void ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_inBT2::reset() {
-	m_sm.reset();
-
-	// update scalar inputs
-	m_sm.inputdata_AGen_Start_X_Addr = getMappedRegValue<32>("AGen_Start_X_Addr");
-	m_sm.inputdata_AGen_Offset_0 = getMappedRegValue<31>("AGen_Offset_0");
-	m_sm.inputdata_AGen_CmdSize = getMappedRegValue<8>("AGen_CmdSize");
-	m_sm.inputdata_AGen_Wrap_X = getMappedRegValue<32>("AGen_Wrap_X");
-	m_sm.inputdata_AGen_BlockSize_X = getMappedRegValue<33>("AGen_BlockSize_X");
-	m_sm.inputdata_AGen_Addr_En = getMappedRegValue<1>("AGen_Addr_En");
-
-
-
-
-	// reset push outputs
-	m_output_cgen_out_0.reset();
-}
-
-bool ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_inBT2::runCycle() {
-
-
-
-	// push outputs - pass through stall signal
-	m_sm.outputstall_cgen_out_0 = varint_u<1>(m_output_cgen_out_0.stalled());
-
-	// update scalar inputs
-	m_sm.inputdata_AGen_Start_X_Addr = getMappedRegValue<32>("AGen_Start_X_Addr");
-	m_sm.inputdata_AGen_Offset_0 = getMappedRegValue<31>("AGen_Offset_0");
-	m_sm.inputdata_AGen_CmdSize = getMappedRegValue<8>("AGen_CmdSize");
-	m_sm.inputdata_AGen_Wrap_X = getMappedRegValue<32>("AGen_Wrap_X");
-	m_sm.inputdata_AGen_BlockSize_X = getMappedRegValue<33>("AGen_BlockSize_X");
-	m_sm.inputdata_AGen_Addr_En = getMappedRegValue<1>("AGen_Addr_En");
-
-	// run the state machine
-	m_sm.execute();
-
-	// update inputs/outputs/signals..
-
-
-
-	// update push outputs
-	m_output_cgen_out_0.valid = m_sm.outputvalid_cgen_out_0;
-	try {
-		if (m_output_cgen_out_0.valid)
-			m_output_cgen_out_0.push_back(varint_u<64>(m_sm.outputdata_cgen_out_0));
-	} catch (SimException) {
-		throw SimException("Push output 'cgen_out_0' in state machine 'Manager_addrgen_cmd_MemoryControllerPro0_inBT2' is full");
-	}
-	m_output_cgen_out_0.setOutputStalled(isPushOutputStalled(m_output_cgen_out_0.port));
-	if (m_output_cgen_out_0.haveData() && !isPushOutputStalled(m_output_cgen_out_0.port)) {
-		pushOutput(m_output_cgen_out_0.port, m_output_cgen_out_0.peek());
-		m_output_cgen_out_0.pop_front();
-	}
-
-
-	getDebugStreams()->finishCycle();
-	return true;
-}
-
-
-
-}}
-

tests/StreamFMA_MAX5C_DFE_SIM/scratch/software-sim/build/StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_inBT2.h

@@ -1,70 +0,0 @@
-#pragma once
-
-#include <string>
-
-#include "ManagerSync.h"
-#include "Debuggable.h"
-#include "SimException.h"
-#include "Connections.h"
-#include "MappedElementInterface.h"
-#include "ManagerStateMachine_IO.h"
-#include "PushSync.h"
-#include <deque>
-
-#include "StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_inBT2.h"
-
-namespace maxcompilersim {
-namespace state_machine {
-
-class ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_inBT2
-	: public Debuggable, public MappedElementInterface
-	, public PushSourceSync
-{
-public:
-	ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_inBT2(const std::string &name);
-	
-	virtual bool runCycle();
-	virtual void reset();
-	
-
-protected:
-
-private:
-	Manager_addrgen_cmd_MemoryControllerPro0_inBT2 m_sm;
-
-	template<uint dataWidth>
-	varint_u<dataWidth> getMappedRegValue(const char *name) {
-		MappedRegisterPtr reg(getMappedReg(name));
-		return varint_u<dataWidth>(reg->getData());
-	}
-
-
-
-
-
-	PushOutput m_output_cgen_out_0;
-	
-	// Java Sim accessing methods
-	Data getMappedMemValue(const std::string &name, const uint width, const uint entry) {
-		AbstractMappedMemoryPtr mem(getMappedMem(name));
-		return mem->getData(entry);
-	}
-	
-	void setMappedMemValue(const std::string &name, const uint entry, const Data &data) {
-		AbstractMappedMemoryPtr mem(getMappedMem(name));
-		mem->setData(entry, data);
-	}
-
-	Data getMappedRegValue(const std::string &name, const uint width) {
-		MappedRegisterPtr reg(getMappedReg(name));
-		return reg->getData();
-	}
-
-	void setMappedRegValue(const std::string &name, const Data &data) {
-		MappedRegisterPtr reg(getMappedReg(name));
-		reg->setData(data);
-	}
-};
-
-}}
-

tests/StreamFMA_MAX5C_DFE_SIM/scratch/software-sim/build/StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_inBT3.cpp

@@ -1,84 +0,0 @@
-#include "StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_inBT3.h"
-
-namespace maxcompilersim {
-namespace state_machine {
-
-ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_inBT3::ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_inBT3(const std::string &name)
-	: ManagerBlockSync(name)
-	, Debuggable(this, name)
-	, m_sm(getDebugStreams(), 0)
-	, m_output_cgen_out_0(registerPushOutput("cgen_out_0"), 64, 1)
-{
-	// register scalar inputs
-	registerMappedRegister("AGen_Start_X_Addr", Data(32));
-	registerMappedRegister("AGen_Offset_0", Data(31));
-	registerMappedRegister("AGen_CmdSize", Data(8));
-	registerMappedRegister("AGen_Wrap_X", Data(32));
-	registerMappedRegister("AGen_BlockSize_X", Data(33));
-	registerMappedRegister("AGen_Addr_En", Data(1));
-
-}
-
-void ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_inBT3::reset() {
-	m_sm.reset();
-
-	// update scalar inputs
-	m_sm.inputdata_AGen_Start_X_Addr = getMappedRegValue<32>("AGen_Start_X_Addr");
-	m_sm.inputdata_AGen_Offset_0 = getMappedRegValue<31>("AGen_Offset_0");
-	m_sm.inputdata_AGen_CmdSize = getMappedRegValue<8>("AGen_CmdSize");
-	m_sm.inputdata_AGen_Wrap_X = getMappedRegValue<32>("AGen_Wrap_X");
-	m_sm.inputdata_AGen_BlockSize_X = getMappedRegValue<33>("AGen_BlockSize_X");
-	m_sm.inputdata_AGen_Addr_En = getMappedRegValue<1>("AGen_Addr_En");
-
-
-
-
-	// reset push outputs
-	m_output_cgen_out_0.reset();
-}
-
-bool ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_inBT3::runCycle() {
-
-
-
-	// push outputs - pass through stall signal
-	m_sm.outputstall_cgen_out_0 = varint_u<1>(m_output_cgen_out_0.stalled());
-
-	// update scalar inputs
-	m_sm.inputdata_AGen_Start_X_Addr = getMappedRegValue<32>("AGen_Start_X_Addr");
-	m_sm.inputdata_AGen_Offset_0 = getMappedRegValue<31>("AGen_Offset_0");
-	m_sm.inputdata_AGen_CmdSize = getMappedRegValue<8>("AGen_CmdSize");
-	m_sm.inputdata_AGen_Wrap_X = getMappedRegValue<32>("AGen_Wrap_X");
-	m_sm.inputdata_AGen_BlockSize_X = getMappedRegValue<33>("AGen_BlockSize_X");
-	m_sm.inputdata_AGen_Addr_En = getMappedRegValue<1>("AGen_Addr_En");
-
-	// run the state machine
-	m_sm.execute();
-
-	// update inputs/outputs/signals..
-
-
-
-	// update push outputs
-	m_output_cgen_out_0.valid = m_sm.outputvalid_cgen_out_0;
-	try {
-		if (m_output_cgen_out_0.valid)
-			m_output_cgen_out_0.push_back(varint_u<64>(m_sm.outputdata_cgen_out_0));
-	} catch (SimException) {
-		throw SimException("Push output 'cgen_out_0' in state machine 'Manager_addrgen_cmd_MemoryControllerPro0_inBT3' is full");
-	}
-	m_output_cgen_out_0.setOutputStalled(isPushOutputStalled(m_output_cgen_out_0.port));
-	if (m_output_cgen_out_0.haveData() && !isPushOutputStalled(m_output_cgen_out_0.port)) {
-		pushOutput(m_output_cgen_out_0.port, m_output_cgen_out_0.peek());
-		m_output_cgen_out_0.pop_front();
-	}
-
-
-	getDebugStreams()->finishCycle();
-	return true;
-}
-
-
-
-}}
-

tests/StreamFMA_MAX5C_DFE_SIM/scratch/software-sim/build/StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_inBT3.h

@@ -1,70 +0,0 @@
-#pragma once
-
-#include <string>
-
-#include "ManagerSync.h"
-#include "Debuggable.h"
-#include "SimException.h"
-#include "Connections.h"
-#include "MappedElementInterface.h"
-#include "ManagerStateMachine_IO.h"
-#include "PushSync.h"
-#include <deque>
-
-#include "StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_inBT3.h"
-
-namespace maxcompilersim {
-namespace state_machine {
-
-class ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_inBT3
-	: public Debuggable, public MappedElementInterface
-	, public PushSourceSync
-{
-public:
-	ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_inBT3(const std::string &name);
-	
-	virtual bool runCycle();
-	virtual void reset();
-	
-
-protected:
-
-private:
-	Manager_addrgen_cmd_MemoryControllerPro0_inBT3 m_sm;
-
-	template<uint dataWidth>
-	varint_u<dataWidth> getMappedRegValue(const char *name) {
-		MappedRegisterPtr reg(getMappedReg(name));
-		return varint_u<dataWidth>(reg->getData());
-	}
-
-
-
-
-
-	PushOutput m_output_cgen_out_0;
-	
-	// Java Sim accessing methods
-	Data getMappedMemValue(const std::string &name, const uint width, const uint entry) {
-		AbstractMappedMemoryPtr mem(getMappedMem(name));
-		return mem->getData(entry);
-	}
-	
-	void setMappedMemValue(const std::string &name, const uint entry, const Data &data) {
-		AbstractMappedMemoryPtr mem(getMappedMem(name));
-		mem->setData(entry, data);
-	}
-
-	Data getMappedRegValue(const std::string &name, const uint width) {
-		MappedRegisterPtr reg(getMappedReg(name));
-		return reg->getData();
-	}
-
-	void setMappedRegValue(const std::string &name, const Data &data) {
-		MappedRegisterPtr reg(getMappedReg(name));
-		reg->setData(data);
-	}
-};
-
-}}
-

tests/StreamFMA_MAX5C_DFE_SIM/scratch/software-sim/build/StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_oDataT1.cpp

@@ -1,84 +0,0 @@
-#include "StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_oDataT1.h"
-
-namespace maxcompilersim {
-namespace state_machine {
-
-ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_oDataT1::ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_oDataT1(const std::string &name)
-	: ManagerBlockSync(name)
-	, Debuggable(this, name)
-	, m_sm(getDebugStreams(), 0)
-	, m_output_cgen_out_0(registerPushOutput("cgen_out_0"), 64, 1)
-{
-	// register scalar inputs
-	registerMappedRegister("AGen_Start_X_Addr", Data(32));
-	registerMappedRegister("AGen_Offset_0", Data(31));
-	registerMappedRegister("AGen_CmdSize", Data(8));
-	registerMappedRegister("AGen_Wrap_X", Data(32));
-	registerMappedRegister("AGen_BlockSize_X", Data(33));
-	registerMappedRegister("AGen_Addr_En", Data(1));
-
-}
-
-void ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_oDataT1::reset() {
-	m_sm.reset();
-
-	// update scalar inputs
-	m_sm.inputdata_AGen_Start_X_Addr = getMappedRegValue<32>("AGen_Start_X_Addr");
-	m_sm.inputdata_AGen_Offset_0 = getMappedRegValue<31>("AGen_Offset_0");
-	m_sm.inputdata_AGen_CmdSize = getMappedRegValue<8>("AGen_CmdSize");
-	m_sm.inputdata_AGen_Wrap_X = getMappedRegValue<32>("AGen_Wrap_X");
-	m_sm.inputdata_AGen_BlockSize_X = getMappedRegValue<33>("AGen_BlockSize_X");
-	m_sm.inputdata_AGen_Addr_En = getMappedRegValue<1>("AGen_Addr_En");
-
-
-
-
-	// reset push outputs
-	m_output_cgen_out_0.reset();
-}
-
-bool ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_oDataT1::runCycle() {
-
-
-
-	// push outputs - pass through stall signal
-	m_sm.outputstall_cgen_out_0 = varint_u<1>(m_output_cgen_out_0.stalled());
-
-	// update scalar inputs
-	m_sm.inputdata_AGen_Start_X_Addr = getMappedRegValue<32>("AGen_Start_X_Addr");
-	m_sm.inputdata_AGen_Offset_0 = getMappedRegValue<31>("AGen_Offset_0");
-	m_sm.inputdata_AGen_CmdSize = getMappedRegValue<8>("AGen_CmdSize");
-	m_sm.inputdata_AGen_Wrap_X = getMappedRegValue<32>("AGen_Wrap_X");
-	m_sm.inputdata_AGen_BlockSize_X = getMappedRegValue<33>("AGen_BlockSize_X");
-	m_sm.inputdata_AGen_Addr_En = getMappedRegValue<1>("AGen_Addr_En");
-
-	// run the state machine
-	m_sm.execute();
-
-	// update inputs/outputs/signals..
-
-
-
-	// update push outputs
-	m_output_cgen_out_0.valid = m_sm.outputvalid_cgen_out_0;
-	try {
-		if (m_output_cgen_out_0.valid)
-			m_output_cgen_out_0.push_back(varint_u<64>(m_sm.outputdata_cgen_out_0));
-	} catch (SimException) {
-		throw SimException("Push output 'cgen_out_0' in state machine 'Manager_addrgen_cmd_MemoryControllerPro0_oDataT1' is full");
-	}
-	m_output_cgen_out_0.setOutputStalled(isPushOutputStalled(m_output_cgen_out_0.port));
-	if (m_output_cgen_out_0.haveData() && !isPushOutputStalled(m_output_cgen_out_0.port)) {
-		pushOutput(m_output_cgen_out_0.port, m_output_cgen_out_0.peek());
-		m_output_cgen_out_0.pop_front();
-	}
-
-
-	getDebugStreams()->finishCycle();
-	return true;
-}
-
-
-
-}}
-

tests/StreamFMA_MAX5C_DFE_SIM/scratch/software-sim/build/StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_oDataT1.h

@@ -1,70 +0,0 @@
-#pragma once
-
-#include <string>
-
-#include "ManagerSync.h"
-#include "Debuggable.h"
-#include "SimException.h"
-#include "Connections.h"
-#include "MappedElementInterface.h"
-#include "ManagerStateMachine_IO.h"
-#include "PushSync.h"
-#include <deque>
-
-#include "StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_oDataT1.h"
-
-namespace maxcompilersim {
-namespace state_machine {
-
-class ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_oDataT1
-	: public Debuggable, public MappedElementInterface
-	, public PushSourceSync
-{
-public:
-	ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_oDataT1(const std::string &name);
-	
-	virtual bool runCycle();
-	virtual void reset();
-	
-
-protected:
-
-private:
-	Manager_addrgen_cmd_MemoryControllerPro0_oDataT1 m_sm;
-
-	template<uint dataWidth>
-	varint_u<dataWidth> getMappedRegValue(const char *name) {
-		MappedRegisterPtr reg(getMappedReg(name));
-		return varint_u<dataWidth>(reg->getData());
-	}
-
-
-
-
-
-	PushOutput m_output_cgen_out_0;
-	
-	// Java Sim accessing methods
-	Data getMappedMemValue(const std::string &name, const uint width, const uint entry) {
-		AbstractMappedMemoryPtr mem(getMappedMem(name));
-		return mem->getData(entry);
-	}
-	
-	void setMappedMemValue(const std::string &name, const uint entry, const Data &data) {
-		AbstractMappedMemoryPtr mem(getMappedMem(name));
-		mem->setData(entry, data);
-	}
-
-	Data getMappedRegValue(const std::string &name, const uint width) {
-		MappedRegisterPtr reg(getMappedReg(name));
-		return reg->getData();
-	}
-
-	void setMappedRegValue(const std::string &name, const Data &data) {
-		MappedRegisterPtr reg(getMappedReg(name));
-		reg->setData(data);
-	}
-};
-
-}}
-

tests/StreamFMA_MAX5C_DFE_SIM/scratch/software-sim/build/StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_oDataT2.cpp

@@ -1,84 +0,0 @@
-#include "StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_oDataT2.h"
-
-namespace maxcompilersim {
-namespace state_machine {
-
-ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_oDataT2::ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_oDataT2(const std::string &name)
-	: ManagerBlockSync(name)
-	, Debuggable(this, name)
-	, m_sm(getDebugStreams(), 0)
-	, m_output_cgen_out_0(registerPushOutput("cgen_out_0"), 64, 1)
-{
-	// register scalar inputs
-	registerMappedRegister("AGen_Start_X_Addr", Data(32));
-	registerMappedRegister("AGen_Offset_0", Data(31));
-	registerMappedRegister("AGen_CmdSize", Data(8));
-	registerMappedRegister("AGen_Wrap_X", Data(32));
-	registerMappedRegister("AGen_BlockSize_X", Data(33));
-	registerMappedRegister("AGen_Addr_En", Data(1));
-
-}
-
-void ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_oDataT2::reset() {
-	m_sm.reset();
-
-	// update scalar inputs
-	m_sm.inputdata_AGen_Start_X_Addr = getMappedRegValue<32>("AGen_Start_X_Addr");
-	m_sm.inputdata_AGen_Offset_0 = getMappedRegValue<31>("AGen_Offset_0");
-	m_sm.inputdata_AGen_CmdSize = getMappedRegValue<8>("AGen_CmdSize");
-	m_sm.inputdata_AGen_Wrap_X = getMappedRegValue<32>("AGen_Wrap_X");
-	m_sm.inputdata_AGen_BlockSize_X = getMappedRegValue<33>("AGen_BlockSize_X");
-	m_sm.inputdata_AGen_Addr_En = getMappedRegValue<1>("AGen_Addr_En");
-
-
-
-
-	// reset push outputs
-	m_output_cgen_out_0.reset();
-}
-
-bool ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_oDataT2::runCycle() {
-
-
-
-	// push outputs - pass through stall signal
-	m_sm.outputstall_cgen_out_0 = varint_u<1>(m_output_cgen_out_0.stalled());
-
-	// update scalar inputs
-	m_sm.inputdata_AGen_Start_X_Addr = getMappedRegValue<32>("AGen_Start_X_Addr");
-	m_sm.inputdata_AGen_Offset_0 = getMappedRegValue<31>("AGen_Offset_0");
-	m_sm.inputdata_AGen_CmdSize = getMappedRegValue<8>("AGen_CmdSize");
-	m_sm.inputdata_AGen_Wrap_X = getMappedRegValue<32>("AGen_Wrap_X");
-	m_sm.inputdata_AGen_BlockSize_X = getMappedRegValue<33>("AGen_BlockSize_X");
-	m_sm.inputdata_AGen_Addr_En = getMappedRegValue<1>("AGen_Addr_En");
-
-	// run the state machine
-	m_sm.execute();
-
-	// update inputs/outputs/signals..
-
-
-
-	// update push outputs
-	m_output_cgen_out_0.valid = m_sm.outputvalid_cgen_out_0;
-	try {
-		if (m_output_cgen_out_0.valid)
-			m_output_cgen_out_0.push_back(varint_u<64>(m_sm.outputdata_cgen_out_0));
-	} catch (SimException) {
-		throw SimException("Push output 'cgen_out_0' in state machine 'Manager_addrgen_cmd_MemoryControllerPro0_oDataT2' is full");
-	}
-	m_output_cgen_out_0.setOutputStalled(isPushOutputStalled(m_output_cgen_out_0.port));
-	if (m_output_cgen_out_0.haveData() && !isPushOutputStalled(m_output_cgen_out_0.port)) {
-		pushOutput(m_output_cgen_out_0.port, m_output_cgen_out_0.peek());
-		m_output_cgen_out_0.pop_front();
-	}
-
-
-	getDebugStreams()->finishCycle();
-	return true;
-}
-
-
-
-}}
-

tests/StreamFMA_MAX5C_DFE_SIM/scratch/software-sim/build/StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_oDataT2.h

@@ -1,70 +0,0 @@
-#pragma once
-
-#include <string>
-
-#include "ManagerSync.h"
-#include "Debuggable.h"
-#include "SimException.h"
-#include "Connections.h"
-#include "MappedElementInterface.h"
-#include "ManagerStateMachine_IO.h"
-#include "PushSync.h"
-#include <deque>
-
-#include "StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_oDataT2.h"
-
-namespace maxcompilersim {
-namespace state_machine {
-
-class ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_oDataT2
-	: public Debuggable, public MappedElementInterface
-	, public PushSourceSync
-{
-public:
-	ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_oDataT2(const std::string &name);
-	
-	virtual bool runCycle();
-	virtual void reset();
-	
-
-protected:
-
-private:
-	Manager_addrgen_cmd_MemoryControllerPro0_oDataT2 m_sm;
-
-	template<uint dataWidth>
-	varint_u<dataWidth> getMappedRegValue(const char *name) {
-		MappedRegisterPtr reg(getMappedReg(name));
-		return varint_u<dataWidth>(reg->getData());
-	}
-
-
-
-
-
-	PushOutput m_output_cgen_out_0;
-	
-	// Java Sim accessing methods
-	Data getMappedMemValue(const std::string &name, const uint width, const uint entry) {
-		AbstractMappedMemoryPtr mem(getMappedMem(name));
-		return mem->getData(entry);
-	}
-	
-	void setMappedMemValue(const std::string &name, const uint entry, const Data &data) {
-		AbstractMappedMemoryPtr mem(getMappedMem(name));
-		mem->setData(entry, data);
-	}
-
-	Data getMappedRegValue(const std::string &name, const uint width) {
-		MappedRegisterPtr reg(getMappedReg(name));
-		return reg->getData();
-	}
-
-	void setMappedRegValue(const std::string &name, const Data &data) {
-		MappedRegisterPtr reg(getMappedReg(name));
-		reg->setData(data);
-	}
-};
-
-}}
-

tests/StreamFMA_MAX5C_DFE_SIM/scratch/software-sim/build/StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_oDataT3.cpp

@@ -1,84 +0,0 @@
-#include "StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_oDataT3.h"
-
-namespace maxcompilersim {
-namespace state_machine {
-
-ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_oDataT3::ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_oDataT3(const std::string &name)
-	: ManagerBlockSync(name)
-	, Debuggable(this, name)
-	, m_sm(getDebugStreams(), 0)
-	, m_output_cgen_out_0(registerPushOutput("cgen_out_0"), 64, 1)
-{
-	// register scalar inputs
-	registerMappedRegister("AGen_Start_X_Addr", Data(32));
-	registerMappedRegister("AGen_Offset_0", Data(31));
-	registerMappedRegister("AGen_CmdSize", Data(8));
-	registerMappedRegister("AGen_Wrap_X", Data(32));
-	registerMappedRegister("AGen_BlockSize_X", Data(33));
-	registerMappedRegister("AGen_Addr_En", Data(1));
-
-}
-
-void ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_oDataT3::reset() {
-	m_sm.reset();
-
-	// update scalar inputs
-	m_sm.inputdata_AGen_Start_X_Addr = getMappedRegValue<32>("AGen_Start_X_Addr");
-	m_sm.inputdata_AGen_Offset_0 = getMappedRegValue<31>("AGen_Offset_0");
-	m_sm.inputdata_AGen_CmdSize = getMappedRegValue<8>("AGen_CmdSize");
-	m_sm.inputdata_AGen_Wrap_X = getMappedRegValue<32>("AGen_Wrap_X");
-	m_sm.inputdata_AGen_BlockSize_X = getMappedRegValue<33>("AGen_BlockSize_X");
-	m_sm.inputdata_AGen_Addr_En = getMappedRegValue<1>("AGen_Addr_En");
-
-
-
-
-	// reset push outputs
-	m_output_cgen_out_0.reset();
-}
-
-bool ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_oDataT3::runCycle() {
-
-
-
-	// push outputs - pass through stall signal
-	m_sm.outputstall_cgen_out_0 = varint_u<1>(m_output_cgen_out_0.stalled());
-
-	// update scalar inputs
-	m_sm.inputdata_AGen_Start_X_Addr = getMappedRegValue<32>("AGen_Start_X_Addr");
-	m_sm.inputdata_AGen_Offset_0 = getMappedRegValue<31>("AGen_Offset_0");
-	m_sm.inputdata_AGen_CmdSize = getMappedRegValue<8>("AGen_CmdSize");
-	m_sm.inputdata_AGen_Wrap_X = getMappedRegValue<32>("AGen_Wrap_X");
-	m_sm.inputdata_AGen_BlockSize_X = getMappedRegValue<33>("AGen_BlockSize_X");
-	m_sm.inputdata_AGen_Addr_En = getMappedRegValue<1>("AGen_Addr_En");
-
-	// run the state machine
-	m_sm.execute();
-
-	// update inputs/outputs/signals..
-
-
-
-	// update push outputs
-	m_output_cgen_out_0.valid = m_sm.outputvalid_cgen_out_0;
-	try {
-		if (m_output_cgen_out_0.valid)
-			m_output_cgen_out_0.push_back(varint_u<64>(m_sm.outputdata_cgen_out_0));
-	} catch (SimException) {
-		throw SimException("Push output 'cgen_out_0' in state machine 'Manager_addrgen_cmd_MemoryControllerPro0_oDataT3' is full");
-	}
-	m_output_cgen_out_0.setOutputStalled(isPushOutputStalled(m_output_cgen_out_0.port));
-	if (m_output_cgen_out_0.haveData() && !isPushOutputStalled(m_output_cgen_out_0.port)) {
-		pushOutput(m_output_cgen_out_0.port, m_output_cgen_out_0.peek());
-		m_output_cgen_out_0.pop_front();
-	}
-
-
-	getDebugStreams()->finishCycle();
-	return true;
-}
-
-
-
-}}
-

tests/StreamFMA_MAX5C_DFE_SIM/scratch/software-sim/build/StateMachineManagerBlock_impl_addrgen_cmd_MemoryControllerPro0_oDataT3.h

@@ -1,70 +0,0 @@
-#pragma once
-
-#include <string>
-
-#include "ManagerSync.h"
-#include "Debuggable.h"
-#include "SimException.h"
-#include "Connections.h"
-#include "MappedElementInterface.h"
-#include "ManagerStateMachine_IO.h"
-#include "PushSync.h"
-#include <deque>
-
-#include "StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_oDataT3.h"
-
-namespace maxcompilersim {
-namespace state_machine {
-
-class ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_oDataT3
-	: public Debuggable, public MappedElementInterface
-	, public PushSourceSync
-{
-public:
-	ManagerBlockSM_addrgen_cmd_MemoryControllerPro0_oDataT3(const std::string &name);
-	
-	virtual bool runCycle();
-	virtual void reset();
-	
-
-protected:
-
-private:
-	Manager_addrgen_cmd_MemoryControllerPro0_oDataT3 m_sm;
-
-	template<uint dataWidth>
-	varint_u<dataWidth> getMappedRegValue(const char *name) {
-		MappedRegisterPtr reg(getMappedReg(name));
-		return varint_u<dataWidth>(reg->getData());
-	}
-
-
-
-
-
-	PushOutput m_output_cgen_out_0;
-	
-	// Java Sim accessing methods
-	Data getMappedMemValue(const std::string &name, const uint width, const uint entry) {
-		AbstractMappedMemoryPtr mem(getMappedMem(name));
-		return mem->getData(entry);
-	}
-	
-	void setMappedMemValue(const std::string &name, const uint entry, const Data &data) {
-		AbstractMappedMemoryPtr mem(getMappedMem(name));
-		mem->setData(entry, data);
-	}
-
-	Data getMappedRegValue(const std::string &name, const uint width) {
-		MappedRegisterPtr reg(getMappedReg(name));
-		return reg->getData();
-	}
-
-	void setMappedRegValue(const std::string &name, const Data &data) {
-		MappedRegisterPtr reg(getMappedReg(name));
-		reg->setData(data);
-	}
-};
-
-}}
-

tests/StreamFMA_MAX5C_DFE_SIM/scratch/software-sim/build/StateMachine_impl_M_MemoryControllerPro0.h

@@ -1,251 +0,0 @@
-#ifndef MANAGER_STATE_MACHINE_IMPL_MemoryControllerPro0_H
-#define MANAGER_STATE_MACHINE_IMPL_MemoryControllerPro0_H
-
-#include "HWTypes.h"
-#include "Debuggable.h"
-#include "StateMachine_FIFO.h"
-
-namespace maxcompilersim {
-namespace state_machine {
-
-class Manager_MemoryControllerPro0 {
-public:
-	Manager_MemoryControllerPro0(maxcompilersim::DebugStreams *debug_output, int node_number);
-	void reset();
-	void execute() {execute(true, false);}
-	void execute(bool sm_not_flushing, bool stall);
-
-	// pull inputs
-	varint_u<512> inputdata_read_stream_maxj_a;
-	varint_u<1> inputempty_read_stream_maxj_a;
-	varint_u<1> inputalmost_empty_read_stream_maxj_a;
-	varint_u<1> inputread_read_stream_maxj_a;
-	varint_u<512> inputdata_read_stream_maxj_b;
-	varint_u<1> inputempty_read_stream_maxj_b;
-	varint_u<1> inputalmost_empty_read_stream_maxj_b;
-	varint_u<1> inputread_read_stream_maxj_b;
-	varint_u<512> inputdata_read_stream_maxj_c;
-	varint_u<1> inputempty_read_stream_maxj_c;
-	varint_u<1> inputalmost_empty_read_stream_maxj_c;
-	varint_u<1> inputread_read_stream_maxj_c;
-
-	// pull outputs
-	varint_u<1536> outputdata_read_0;
-	varint_u<1> outputempty_read_0;
-	varint_u<1> outputalmost_empty_read_0;
-	varint_u<1> outputread_read_0;
-	varint_u<1536> outputdata_read_1;
-	varint_u<1> outputempty_read_1;
-	varint_u<1> outputalmost_empty_read_1;
-	varint_u<1> outputread_read_1;
-	varint_u<1536> outputdata_read_2;
-	varint_u<1> outputempty_read_2;
-	varint_u<1> outputalmost_empty_read_2;
-	varint_u<1> outputread_read_2;
-	varint_u<1536> outputdata_read_3;
-	varint_u<1> outputempty_read_3;
-	varint_u<1> outputalmost_empty_read_3;
-	varint_u<1> outputread_read_3;
-
-	// push inputs
-	varint_u<64> inputdata_read_command_0;
-	varint_u<1> inputvalid_read_command_0;
-	varint_u<1> inputstall_read_command_0;
-	varint_u<64> inputdata_read_command_1;
-	varint_u<1> inputvalid_read_command_1;
-	varint_u<1> inputstall_read_command_1;
-	varint_u<64> inputdata_read_command_2;
-	varint_u<1> inputvalid_read_command_2;
-	varint_u<1> inputstall_read_command_2;
-	varint_u<64> inputdata_read_command_3;
-	varint_u<1> inputvalid_read_command_3;
-	varint_u<1> inputstall_read_command_3;
-	varint_u<1536> inputdata_write_0;
-	varint_u<1> inputvalid_write_0;
-	varint_u<1> inputstall_write_0;
-	varint_u<1536> inputdata_write_1;
-	varint_u<1> inputvalid_write_1;
-	varint_u<1> inputstall_write_1;
-	varint_u<64> inputdata_write_command_0;
-	varint_u<1> inputvalid_write_command_0;
-	varint_u<1> inputstall_write_command_0;
-	varint_u<64> inputdata_write_command_1;
-	varint_u<1> inputvalid_write_command_1;
-	varint_u<1> inputstall_write_command_1;
-
-	// push outputs
-	varint_u<1> outputdata_Tag_Out;
-	varint_u<1> outputvalid_Tag_Out;
-	varint_u<1> outputstall_Tag_Out;
-	varint_u<544> outputdata_cmd_stream_maxj_a;
-	varint_u<1> outputvalid_cmd_stream_maxj_a;
-	varint_u<1> outputstall_cmd_stream_maxj_a;
-	varint_u<544> outputdata_cmd_stream_maxj_b;
-	varint_u<1> outputvalid_cmd_stream_maxj_b;
-	varint_u<1> outputstall_cmd_stream_maxj_b;
-	varint_u<544> outputdata_cmd_stream_maxj_c;
-	varint_u<1> outputvalid_cmd_stream_maxj_c;
-	varint_u<1> outputstall_cmd_stream_maxj_c;
-
-	// scalar inputs
-	varint_u<6> inputdata_Mcp_Int_Disable_OR;
-	varint_u<6> inputdata_Mcp_Int_Enable_AND;
-
-private:
-	maxcompilersim::DebugStreams *m_debug_output;
-	int m_node_number;
-
-	// integer state
-	varint_u<1> state1_m_newCommandSignal_MemoryControllerPro0_clk;
-	varint_u<1> state2_m_transfersCompleted_MemoryControllerPro0_clk;
-	varint_u<1> state3_PipelinedFifo_fifoValid_MemoryControllerPro0_clk;
-	varint_u<70> state4_PipelinedFifo_regIn_MemoryControllerPro0_clk;
-	varint_u<1> state5_PipelinedFifo_regInValid_MemoryControllerPro0_clk;
-	varint_u<70> state6_PipelinedFifo_regOut_MemoryControllerPro0_clk;
-	varint_u<1> state7_PipelinedFifo_regOutValid_MemoryControllerPro0_clk;
-	varint_u<1> state8_PipelinedFifo_progFull_MemoryControllerPro0_clk;
-	varint_u<3> state9_m_arbitrationDelayCounter_MemoryControllerPro0_clk;
-	varint_u<1> state10_PipelinedFifo_fifoValid_MemoryControllerPro0_clk;
-	varint_u<64> state11_PipelinedFifo_regIn_MemoryControllerPro0_clk;
-	varint_u<1> state12_PipelinedFifo_regInValid_MemoryControllerPro0_clk;
-	varint_u<64> state13_PipelinedFifo_regOut_MemoryControllerPro0_clk;
-	varint_u<1> state14_PipelinedFifo_regOutValid_MemoryControllerPro0_clk;
-	varint_u<1> state15_PipelinedFifo_progFull_MemoryControllerPro0_clk;
-	varint_u<64> state16_MemoryControllerPro0_clk;
-	varint_u<64> state17_MemoryControllerPro0_clk;
-	varint_u<1> state18_MemoryControllerPro0_clk;
-	varint_u<1> state19_MemoryControllerPro0_clk;
-	varint_u<9> state20_read_fifo_fill_0_MemoryControllerPro0_clk;
-	varint_u<1> state21_Has_Consumed_Read_Data_MemoryControllerPro0_clk;
-	varint_u<1> state22_PipelinedFifo_fifoValid_MemoryControllerPro0_clk;
-	varint_u<64> state23_PipelinedFifo_regIn_MemoryControllerPro0_clk;
-	varint_u<1> state24_PipelinedFifo_regInValid_MemoryControllerPro0_clk;
-	varint_u<64> state25_PipelinedFifo_regOut_MemoryControllerPro0_clk;
-	varint_u<1> state26_PipelinedFifo_regOutValid_MemoryControllerPro0_clk;
-	varint_u<1> state27_PipelinedFifo_progFull_MemoryControllerPro0_clk;
-	varint_u<64> state28_MemoryControllerPro0_clk;
-	varint_u<64> state29_MemoryControllerPro0_clk;
-	varint_u<1> state30_MemoryControllerPro0_clk;
-	varint_u<1> state31_MemoryControllerPro0_clk;
-	varint_u<9> state32_read_fifo_fill_1_MemoryControllerPro0_clk;
-	varint_u<1> state33_Has_Consumed_Read_Data_MemoryControllerPro0_clk;
-	varint_u<1> state34_PipelinedFifo_fifoValid_MemoryControllerPro0_clk;
-	varint_u<64> state35_PipelinedFifo_regIn_MemoryControllerPro0_clk;
-	varint_u<1> state36_PipelinedFifo_regInValid_MemoryControllerPro0_clk;
-	varint_u<64> state37_PipelinedFifo_regOut_MemoryControllerPro0_clk;
-	varint_u<1> state38_PipelinedFifo_regOutValid_MemoryControllerPro0_clk;
-	varint_u<1> state39_PipelinedFifo_progFull_MemoryControllerPro0_clk;
-	varint_u<64> state40_MemoryControllerPro0_clk;
-	varint_u<64> state41_MemoryControllerPro0_clk;
-	varint_u<1> state42_MemoryControllerPro0_clk;
-	varint_u<1> state43_MemoryControllerPro0_clk;
-	varint_u<9> state44_read_fifo_fill_2_MemoryControllerPro0_clk;
-	varint_u<1> state45_Has_Consumed_Read_Data_MemoryControllerPro0_clk;
-	varint_u<1> state46_PipelinedFifo_fifoValid_MemoryControllerPro0_clk;
-	varint_u<64> state47_PipelinedFifo_regIn_MemoryControllerPro0_clk;
-	varint_u<1> state48_PipelinedFifo_regInValid_MemoryControllerPro0_clk;
-	varint_u<64> state49_PipelinedFifo_regOut_MemoryControllerPro0_clk;
-	varint_u<1> state50_PipelinedFifo_regOutValid_MemoryControllerPro0_clk;
-	varint_u<1> state51_PipelinedFifo_progFull_MemoryControllerPro0_clk;
-	varint_u<64> state52_MemoryControllerPro0_clk;
-	varint_u<64> state53_MemoryControllerPro0_clk;
-	varint_u<1> state54_MemoryControllerPro0_clk;
-	varint_u<1> state55_MemoryControllerPro0_clk;
-	varint_u<9> state56_read_fifo_fill_3_MemoryControllerPro0_clk;
-	varint_u<1> state57_Has_Consumed_Read_Data_MemoryControllerPro0_clk;
-	varint_u<1> state58_PipelinedFifo_fifoValid_MemoryControllerPro0_clk;
-	varint_u<1008> state59_PipelinedFifo_regIn_STREAM;
-	varint_u<1> state60_PipelinedFifo_regInValid_STREAM;
-	varint_u<1008> state61_PipelinedFifo_regOut_MemoryControllerPro0_clk;
-	varint_u<1> state62_PipelinedFifo_regOutValid_MemoryControllerPro0_clk;
-	varint_u<1> state63_PipelinedFifo_progFull_STREAM;
-	varint_u<1> state64_PipelinedFifo_fifoValid_MemoryControllerPro0_clk;
-	varint_u<528> state65_PipelinedFifo_regIn_STREAM;
-	varint_u<1> state66_PipelinedFifo_regInValid_STREAM;
-	varint_u<528> state67_PipelinedFifo_regOut_MemoryControllerPro0_clk;
-	varint_u<1> state68_PipelinedFifo_regOutValid_MemoryControllerPro0_clk;
-	varint_u<1> state69_PipelinedFifo_progFull_STREAM;
-	varint_u<1> state70_PipelinedFifo_fifoValid_MemoryControllerPro0_clk;
-	varint_u<64> state71_PipelinedFifo_regIn_MemoryControllerPro0_clk;
-	varint_u<1> state72_PipelinedFifo_regInValid_MemoryControllerPro0_clk;
-	varint_u<64> state73_PipelinedFifo_regOut_MemoryControllerPro0_clk;
-	varint_u<1> state74_PipelinedFifo_regOutValid_MemoryControllerPro0_clk;
-	varint_u<1> state75_PipelinedFifo_progFull_MemoryControllerPro0_clk;
-	varint_u<64> state76_MemoryControllerPro0_clk;
-	varint_u<64> state77_MemoryControllerPro0_clk;
-	varint_u<1> state78_MemoryControllerPro0_clk;
-	varint_u<1> state79_MemoryControllerPro0_clk;
-	varint_u<9> state80_write_fifo_fill_0_MemoryControllerPro0_clk;
-	varint_u<1> state81_Consumed_Write_Data_0_MemoryControllerPro0_clk;
-	varint_u<1> state82_PipelinedFifo_fifoValid_MemoryControllerPro0_clk;
-	varint_u<1008> state83_PipelinedFifo_regIn_STREAM;
-	varint_u<1> state84_PipelinedFifo_regInValid_STREAM;
-	varint_u<1008> state85_PipelinedFifo_regOut_MemoryControllerPro0_clk;
-	varint_u<1> state86_PipelinedFifo_regOutValid_MemoryControllerPro0_clk;
-	varint_u<1> state87_PipelinedFifo_progFull_STREAM;
-	varint_u<1> state88_PipelinedFifo_fifoValid_MemoryControllerPro0_clk;
-	varint_u<528> state89_PipelinedFifo_regIn_STREAM;
-	varint_u<1> state90_PipelinedFifo_regInValid_STREAM;
-	varint_u<528> state91_PipelinedFifo_regOut_MemoryControllerPro0_clk;
-	varint_u<1> state92_PipelinedFifo_regOutValid_MemoryControllerPro0_clk;
-	varint_u<1> state93_PipelinedFifo_progFull_STREAM;
-	varint_u<1> state94_PipelinedFifo_fifoValid_MemoryControllerPro0_clk;
-	varint_u<64> state95_PipelinedFifo_regIn_MemoryControllerPro0_clk;
-	varint_u<1> state96_PipelinedFifo_regInValid_MemoryControllerPro0_clk;
-	varint_u<64> state97_PipelinedFifo_regOut_MemoryControllerPro0_clk;
-	varint_u<1> state98_PipelinedFifo_regOutValid_MemoryControllerPro0_clk;
-	varint_u<1> state99_PipelinedFifo_progFull_MemoryControllerPro0_clk;
-	varint_u<64> state100_MemoryControllerPro0_clk;
-	varint_u<64> state101_MemoryControllerPro0_clk;
-	varint_u<1> state102_MemoryControllerPro0_clk;
-	varint_u<1> state103_MemoryControllerPro0_clk;
-	varint_u<9> state104_write_fifo_fill_1_MemoryControllerPro0_clk;
-	varint_u<1> state105_Consumed_Write_Data_1_MemoryControllerPro0_clk;
-	varint_u<6> state106_Mcp_Int_Enable_AND_reg_MemoryControllerPro0_clk;
-	varint_u<6> state107_Mcp_Int_Disable_OR_reg_MemoryControllerPro0_clk;
-	varint_u<1> state108_Combined_Tag_i_MemoryControllerPro0_clk;
-	varint_u<6> state109_MemCmd_TagCMD_Hold_MemoryControllerPro0_clk;
-	varint_u<1> state110_Has_TriggeredTag_MemoryControllerPro0_clk;
-	varint_u<1> state111_read_word_trigger_MemoryControllerPro0_clk;
-	varint_u<1> state112_cmd_exec_finished_signal_MemoryControllerPro0_clk;
-	varint_u<1> state113_cmd_exec_initialized_signal_MemoryControllerPro0_clk;
-	varint_u<8> state114_cmd_exec_generated_bursts_counter_MemoryControllerPro0_clk;
-	varint_u<31> state115_cmd_exec_flags_reg_MemoryControllerPro0_clk;
-	varint_u<1> state116_PipelinedFifo_fifoValid_MemoryControllerPro0_clk;
-	varint_u<4> state117_PipelinedFifo_regIn_MemoryControllerPro0_clk;
-	varint_u<1> state118_PipelinedFifo_regInValid_MemoryControllerPro0_clk;
-	varint_u<4> state119_PipelinedFifo_regOut_MemoryControllerPro0_clk;
-	varint_u<1> state120_PipelinedFifo_regOutValid_MemoryControllerPro0_clk;
-	varint_u<1> state121_PipelinedFifo_progFull_MemoryControllerPro0_clk;
-	varint_u<3> state122_arb_rr_counter_MemoryControllerPro0_clk;
-	varint_u<3> state123_Next_Arbitrated_Command_MemoryControllerPro0_clk;
-	varint_u<1> state124_Next_Arb_Trigger_MemoryControllerPro0_clk;
-	varint_u<70> state125_Current_Command_MemoryControllerPro0_clk;
-
-	// DUAL CLOCK FIFOs
-	StateMachineDualClockFifo<70, 70, 16, 0, 5> dualFifo_0;
-	StateMachineDualClockFifo<1008, 1008, 512, 0, 10> dualFifo_1;
-	StateMachineDualClockFifo<528, 528, 512, 0, 10> dualFifo_2;
-	StateMachineDualClockFifo<64, 64, 32, 0, 6> dualFifo_3;
-	StateMachineDualClockFifo<1008, 1008, 512, 0, 10> dualFifo_4;
-	StateMachineDualClockFifo<528, 528, 512, 0, 10> dualFifo_5;
-	StateMachineDualClockFifo<64, 64, 32, 0, 6> dualFifo_6;
-	StateMachineDualClockFifo<1008, 1008, 512, 0, 10> dualFifo_7;
-	StateMachineDualClockFifo<528, 528, 512, 0, 10> dualFifo_8;
-	StateMachineDualClockFifo<64, 64, 32, 0, 6> dualFifo_9;
-	StateMachineDualClockFifo<1008, 1008, 512, 0, 10> dualFifo_10;
-	StateMachineDualClockFifo<528, 528, 512, 0, 10> dualFifo_11;
-	StateMachineDualClockFifo<64, 64, 32, 0, 6> dualFifo_12;
-	StateMachineDualClockFifo<1008, 1008, 512, 0, 10> dualFifo_13;
-	StateMachineDualClockFifo<528, 528, 512, 0, 10> dualFifo_14;
-	StateMachineDualClockFifo<64, 64, 32, 0, 6> dualFifo_15;
-	StateMachineDualClockFifo<1008, 1008, 512, 0, 10> dualFifo_16;
-	StateMachineDualClockFifo<528, 528, 512, 0, 10> dualFifo_17;
-	StateMachineDualClockFifo<64, 64, 32, 0, 6> dualFifo_18;
-	StateMachineDualClockFifo<4, 4, 1024, 0, 11> dualFifo_19;
-};
-
-}
-}
-
-#endif // !defined(MANAGER_STATE_MACHINE_IMPL_MemoryControllerPro0_H)

tests/StreamFMA_MAX5C_DFE_SIM/scratch/software-sim/build/StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_inAT2.cpp

@@ -1,230 +0,0 @@
-#include "StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_inAT2.h"
-#include "SimException.h"
-
-namespace {
-
-	using maxcompilersim::varint_u;
-	using maxcompilersim::varint_s;
-
-	template<uint size>
-	varint_u<size> leading1detect(const varint_u<size> &x) {
-		varint_u<size> r;
-
-		for (uint i = 0; i < size; ++i) {
-			uint j = size - 1 - i;
-
-			if (x.get_bit(j)) {
-				r.set_bit(j, true);
-				break;
-			}
-		}
-
-		return r;
-	}
-
-	template<uint size>
-	varint_s<size> leading1detect(const varint_s<size> &x) {
-		varint_s<size> r;
-
-		for (uint i = 0; i < size; ++i) {
-			uint j = size - 1 - i;
-
-			if (x.get_bit(j)) {
-				r.set_bit(j, true);
-				break;
-			}
-		}
-
-		return r;
-	}
-
-	template<uint size>
-	varint_u<size> trailing1detect(const varint_u<size> &x) {
-		varint_u<size> r;
-
-		for (uint i = 0; i < size; ++i) {
-			if (x.get_bit(i)) {
-				r.set_bit(i, true);
-				break;
-			}
-		}
-
-		return r;
-	}
-
-	template<uint size>
-	varint_s<size> trailing1detect(const varint_s<size> &x) {
-		varint_s<size> r;
-
-		for (uint i = 0; i < size; ++i) {
-			if (x.get_bit(i)) {
-				r.set_bit(i, true);
-				break;
-			}
-		}
-
-		return r;
-	}
-
-	template<uint size, uint result_size>
-	varint_u<result_size> one_hot_decode(const varint_u<size> &x) {
-		varint_u<result_size> r;
-
-		for (uint i = 0; i < size; ++i) {
-			if (x.get_bit(i)) {
-				r.set_bits(0, result_size, i);
-				break;
-			}
-		}
-
-		return r;
-	}
-
-	template<uint size, uint result_size>
-	varint_u<result_size> one_hot_encode(const varint_u<size> &x) {
-		varint_u<result_size> r;
-
-		r.set_bit(x.toUInt64(), true);
-
-		return r;
-	}
-
-	template<uint size, uint result_size>
-	varint_s<result_size> one_hot_encode(const varint_s<size> &x) {
-		varint_s<result_size> r;
-
-		r.set_bit(x.toUInt64(), true);
-
-		return r;
-	}
-
-	template<uint size>
-	varint_u<size> reverse(const varint_u<size> &x) {
-		varint_u<size> r;
-
-		for (uint i = 0; i < size; ++i)
-			r.set_bit(i, x.get_bit(size - 1 - i));
-
-		return r;
-	}
-
-	template<uint size>
-	varint_s<size> reverse(const varint_s<size> &x) {
-		varint_s<size> r;
-
-		for (uint i = 0; i < size; ++i)
-			r.set_bit(i, x.get_bit(size - 1 - i));
-
-		return r;
-	}
-}
-maxcompilersim::state_machine::Manager_addrgen_cmd_MemoryControllerPro0_inAT2::Manager_addrgen_cmd_MemoryControllerPro0_inAT2(maxcompilersim::DebugStreams *debug_output, int node_number) :
-m_debug_output(debug_output),
-m_node_number(node_number),
-state8(0),
-state9(0),
-state10(0),
-state11(0),
-state12(0),
-state3(0)
-{ }
-
-
-
-void
-maxcompilersim::state_machine::Manager_addrgen_cmd_MemoryControllerPro0_inAT2::reset() {
-	state8 = 0;
-	state9 = 0;
-	state10 = 0;
-	state11 = 0;
-	state12 = 0;
-	state3 = 0;
-}
-
-
-
-void
-maxcompilersim::state_machine::Manager_addrgen_cmd_MemoryControllerPro0_inAT2::execute(const bool sm_not_flushing, const bool stall) {
-	varint_u<1> varint_sm_not_flushing(sm_not_flushing);
-	varint_u<1> next_state1(state1);
-	varint_u<31> next_state2(state2);
-	varint_u<33> next_state4(state4);
-	varint_u<32> next_state5(state5);
-	varint_u<32> next_state6(state6);
-	varint_u<8> next_state7(state7);
-	varint_u<32> next_state8(state8);
-	varint_u<32> next_state9(state9);
-	varint_u<32> next_state10(state10);
-	varint_u<1> next_state11(state11);
-	varint_u<8> next_state12(state12);
-	varint_u<2> next_state3(state3);
-	
-	varint_u<8> assignableVar1;
-	
-	next_state1 = inputdata_AGen_Addr_En;
-	next_state2 = inputdata_AGen_Offset_0;
-	next_state4 = inputdata_AGen_BlockSize_X;
-	next_state5 = inputdata_AGen_Wrap_X;
-	next_state6 = inputdata_AGen_Start_X_Addr;
-	next_state7 = inputdata_AGen_CmdSize;
-	outputdata_cgen_out_0 = varint_u<64>(0x0l);
-	outputvalid_cgen_out_0 = varint_u<1>(0x0l);
-	switch (static_cast<int>(state3)) {
-		case 0:
-			next_state8 = state6;
-			next_state9 = state6;
-			next_state10 = varint_u<32>(state4);
-			if (varint_u<1>(state1 != varint_u<1>(0x0l))) {
-				next_state3 = varint_u<2>(0x1l);
-			}
-			break;
-		case 1:
-			next_state9 = state8;
-			assignableVar1 = state7;
-			if (varint_u<1>(state10 < varint_u<32>(assignableVar1))) {
-				assignableVar1 = varint_u<8>(state10);
-			}
-			if (varint_u<1>((state5 - state8) < varint_u<32>(assignableVar1)) & varint_u<1>((state5 - state8) < state10)) {
-				assignableVar1 = varint_u<8>(state5 - state8);
-				next_state8 = varint_u<32>(0x0l);
-			} else {
-				next_state8 = state8 + varint_u<32>(assignableVar1);
-				if (varint_u<1>(state8 >= varint_u<32>(0x80000000l))) {
-					next_state8 = varint_u<32>(0x7fffffffl) & state8;
-				}
-			}
-			next_state10 = state10 - varint_u<32>(assignableVar1);
-			next_state12 = assignableVar1;
-			next_state11 = varint_u<1>((state10 - varint_u<32>(assignableVar1)) == varint_u<32>(0x0l));
-			next_state3 = varint_u<2>(0x2l);
-			break;
-		case 2:
-			if ((~(varint_u<1>(0x0l) | outputstall_cgen_out_0))) {
-				outputdata_cgen_out_0 = varint_u<1>(state11).cat(varint_u<15>(0x1l)).cat(varint_u<1>(varint_u<1>(0x0l))).cat(varint_u<7>(varint_u<8>(0x1l))).cat(varint_u<8>(state12)).cat(varint_u<1>(0x0l)).cat(varint_u<31>((state9 + varint_u<32>(state2))));
-				outputvalid_cgen_out_0 = (state1).slice<0, 1>();
-				if (state11) {
-					next_state3 = varint_u<2>(0x3l);
-				} else {
-					next_state3 = varint_u<2>(0x1l);
-				}
-			}
-			break;
-	}
-	
-	// update states
-	if (!stall) {
-		state1 = next_state1;
-		state2 = next_state2;
-		state4 = next_state4;
-		state5 = next_state5;
-		state6 = next_state6;
-		state7 = next_state7;
-		state8 = next_state8;
-		state9 = next_state9;
-		state10 = next_state10;
-		state11 = next_state11;
-		state12 = next_state12;
-		state3 = next_state3;
-	}
-	
-}

tests/StreamFMA_MAX5C_DFE_SIM/scratch/software-sim/build/StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_inAT2.h

@@ -1,54 +0,0 @@
-#ifndef MANAGER_STATE_MACHINE_IMPL_addrgen_cmd_MemoryControllerPro0_inAT2_H
-#define MANAGER_STATE_MACHINE_IMPL_addrgen_cmd_MemoryControllerPro0_inAT2_H
-
-#include "HWTypes.h"
-#include "Debuggable.h"
-
-namespace maxcompilersim {
-namespace state_machine {
-
-class Manager_addrgen_cmd_MemoryControllerPro0_inAT2 {
-public:
-	Manager_addrgen_cmd_MemoryControllerPro0_inAT2(maxcompilersim::DebugStreams *debug_output, int node_number);
-	void reset();
-	void execute() {execute(true, false);}
-	void execute(bool sm_not_flushing, bool stall);
-
-	// push outputs
-	varint_u<64> outputdata_cgen_out_0;
-	varint_u<1> outputvalid_cgen_out_0;
-	varint_u<1> outputstall_cgen_out_0;
-
-	// scalar inputs
-	varint_u<1> inputdata_AGen_Addr_En;
-	varint_u<33> inputdata_AGen_BlockSize_X;
-	varint_u<8> inputdata_AGen_CmdSize;
-	varint_u<31> inputdata_AGen_Offset_0;
-	varint_u<32> inputdata_AGen_Start_X_Addr;
-	varint_u<32> inputdata_AGen_Wrap_X;
-
-private:
-	maxcompilersim::DebugStreams *m_debug_output;
-	int m_node_number;
-
-	// integer state
-	varint_u<1> state1;
-	varint_u<31> state2;
-	varint_u<33> state4;
-	varint_u<32> state5;
-	varint_u<32> state6;
-	varint_u<8> state7;
-	varint_u<32> state8;
-	varint_u<32> state9;
-	varint_u<32> state10;
-	varint_u<1> state11;
-	varint_u<8> state12;
-
-	// enum state
-	varint_u<2> state3;
-};
-
-}
-}
-
-#endif // !defined(MANAGER_STATE_MACHINE_IMPL_addrgen_cmd_MemoryControllerPro0_inAT2_H)

tests/StreamFMA_MAX5C_DFE_SIM/scratch/software-sim/build/StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_inAT3.cpp

@@ -1,230 +0,0 @@
-#include "StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_inAT3.h"
-#include "SimException.h"
-
-namespace {
-
-	using maxcompilersim::varint_u;
-	using maxcompilersim::varint_s;
-
-	template<uint size>
-	varint_u<size> leading1detect(const varint_u<size> &x) {
-		varint_u<size> r;
-
-		for (uint i = 0; i < size; ++i) {
-			uint j = size - 1 - i;
-
-			if (x.get_bit(j)) {
-				r.set_bit(j, true);
-				break;
-			}
-		}
-
-		return r;
-	}
-
-	template<uint size>
-	varint_s<size> leading1detect(const varint_s<size> &x) {
-		varint_s<size> r;
-
-		for (uint i = 0; i < size; ++i) {
-			uint j = size - 1 - i;
-
-			if (x.get_bit(j)) {
-				r.set_bit(j, true);
-				break;
-			}
-		}
-
-		return r;
-	}
-
-	template<uint size>
-	varint_u<size> trailing1detect(const varint_u<size> &x) {
-		varint_u<size> r;
-
-		for (uint i = 0; i < size; ++i) {
-			if (x.get_bit(i)) {
-				r.set_bit(i, true);
-				break;
-			}
-		}
-
-		return r;
-	}
-
-	template<uint size>
-	varint_s<size> trailing1detect(const varint_s<size> &x) {
-		varint_s<size> r;
-
-		for (uint i = 0; i < size; ++i) {
-			if (x.get_bit(i)) {
-				r.set_bit(i, true);
-				break;
-			}
-		}
-
-		return r;
-	}
-
-	template<uint size, uint result_size>
-	varint_u<result_size> one_hot_decode(const varint_u<size> &x) {
-		varint_u<result_size> r;
-
-		for (uint i = 0; i < size; ++i) {
-			if (x.get_bit(i)) {
-				r.set_bits(0, result_size, i);
-				break;
-			}
-		}
-
-		return r;
-	}
-
-	template<uint size, uint result_size>
-	varint_u<result_size> one_hot_encode(const varint_u<size> &x) {
-		varint_u<result_size> r;
-
-		r.set_bit(x.toUInt64(), true);
-
-		return r;
-	}
-
-	template<uint size, uint result_size>
-	varint_s<result_size> one_hot_encode(const varint_s<size> &x) {
-		varint_s<result_size> r;
-
-		r.set_bit(x.toUInt64(), true);
-
-		return r;
-	}
-
-	template<uint size>
-	varint_u<size> reverse(const varint_u<size> &x) {
-		varint_u<size> r;
-
-		for (uint i = 0; i < size; ++i)
-			r.set_bit(i, x.get_bit(size - 1 - i));
-
-		return r;
-	}
-
-	template<uint size>
-	varint_s<size> reverse(const varint_s<size> &x) {
-		varint_s<size> r;
-
-		for (uint i = 0; i < size; ++i)
-			r.set_bit(i, x.get_bit(size - 1 - i));
-
-		return r;
-	}
-}
-maxcompilersim::state_machine::Manager_addrgen_cmd_MemoryControllerPro0_inAT3::Manager_addrgen_cmd_MemoryControllerPro0_inAT3(maxcompilersim::DebugStreams *debug_output, int node_number) :
-m_debug_output(debug_output),
-m_node_number(node_number),
-state8(0),
-state9(0),
-state10(0),
-state11(0),
-state12(0),
-state3(0)
-{ }
-
-
-
-void
-maxcompilersim::state_machine::Manager_addrgen_cmd_MemoryControllerPro0_inAT3::reset() {
-	state8 = 0;
-	state9 = 0;
-	state10 = 0;
-	state11 = 0;
-	state12 = 0;
-	state3 = 0;
-}
-
-
-
-void
-maxcompilersim::state_machine::Manager_addrgen_cmd_MemoryControllerPro0_inAT3::execute(const bool sm_not_flushing, const bool stall) {
-	varint_u<1> varint_sm_not_flushing(sm_not_flushing);
-	varint_u<1> next_state1(state1);
-	varint_u<31> next_state2(state2);
-	varint_u<33> next_state4(state4);
-	varint_u<32> next_state5(state5);
-	varint_u<32> next_state6(state6);
-	varint_u<8> next_state7(state7);
-	varint_u<32> next_state8(state8);
-	varint_u<32> next_state9(state9);
-	varint_u<32> next_state10(state10);
-	varint_u<1> next_state11(state11);
-	varint_u<8> next_state12(state12);
-	varint_u<2> next_state3(state3);
-	
-	varint_u<8> assignableVar1;
-	
-	next_state1 = inputdata_AGen_Addr_En;
-	next_state2 = inputdata_AGen_Offset_0;
-	next_state4 = inputdata_AGen_BlockSize_X;
-	next_state5 = inputdata_AGen_Wrap_X;
-	next_state6 = inputdata_AGen_Start_X_Addr;
-	next_state7 = inputdata_AGen_CmdSize;
-	outputdata_cgen_out_0 = varint_u<64>(0x0l);
-	outputvalid_cgen_out_0 = varint_u<1>(0x0l);
-	switch (static_cast<int>(state3)) {
-		case 0:
-			next_state8 = state6;
-			next_state9 = state6;
-			next_state10 = varint_u<32>(state4);
-			if (varint_u<1>(state1 != varint_u<1>(0x0l))) {
-				next_state3 = varint_u<2>(0x1l);
-			}
-			break;
-		case 1:
-			next_state9 = state8;
-			assignableVar1 = state7;
-			if (varint_u<1>(state10 < varint_u<32>(assignableVar1))) {
-				assignableVar1 = varint_u<8>(state10);
-			}
-			if (varint_u<1>((state5 - state8) < varint_u<32>(assignableVar1)) & varint_u<1>((state5 - state8) < state10)) {
-				assignableVar1 = varint_u<8>(state5 - state8);
-				next_state8 = varint_u<32>(0x0l);
-			} else {
-				next_state8 = state8 + varint_u<32>(assignableVar1);
-				if (varint_u<1>(state8 >= varint_u<32>(0x80000000l))) {
-					next_state8 = varint_u<32>(0x7fffffffl) & state8;
-				}
-			}
-			next_state10 = state10 - varint_u<32>(assignableVar1);
-			next_state12 = assignableVar1;
-			next_state11 = varint_u<1>((state10 - varint_u<32>(assignableVar1)) == varint_u<32>(0x0l));
-			next_state3 = varint_u<2>(0x2l);
-			break;
-		case 2:
-			if ((~(varint_u<1>(0x0l) | outputstall_cgen_out_0))) {
-				outputdata_cgen_out_0 = varint_u<1>(state11).cat(varint_u<15>(0x1l)).cat(varint_u<1>(varint_u<1>(0x0l))).cat(varint_u<7>(varint_u<8>(0x1l))).cat(varint_u<8>(state12)).cat(varint_u<1>(0x0l)).cat(varint_u<31>((state9 + varint_u<32>(state2))));
-				outputvalid_cgen_out_0 = (state1).slice<0, 1>();
-				if (state11) {
-					next_state3 = varint_u<2>(0x3l);
-				} else {
-					next_state3 = varint_u<2>(0x1l);
-				}
-			}
-			break;
-	}
-	
-	// update states
-	if (!stall) {
-		state1 = next_state1;
-		state2 = next_state2;
-		state4 = next_state4;
-		state5 = next_state5;
-		state6 = next_state6;
-		state7 = next_state7;
-		state8 = next_state8;
-		state9 = next_state9;
-		state10 = next_state10;
-		state11 = next_state11;
-		state12 = next_state12;
-		state3 = next_state3;
-	}
-	
-}

tests/StreamFMA_MAX5C_DFE_SIM/scratch/software-sim/build/StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_inAT3.h

@@ -1,54 +0,0 @@
-#ifndef MANAGER_STATE_MACHINE_IMPL_addrgen_cmd_MemoryControllerPro0_inAT3_H
-#define MANAGER_STATE_MACHINE_IMPL_addrgen_cmd_MemoryControllerPro0_inAT3_H
-
-#include "HWTypes.h"
-#include "Debuggable.h"
-
-namespace maxcompilersim {
-namespace state_machine {
-
-class Manager_addrgen_cmd_MemoryControllerPro0_inAT3 {
-public:
-	Manager_addrgen_cmd_MemoryControllerPro0_inAT3(maxcompilersim::DebugStreams *debug_output, int node_number);
-	void reset();
-	void execute() {execute(true, false);}
-	void execute(bool sm_not_flushing, bool stall);
-
-	// push outputs
-	varint_u<64> outputdata_cgen_out_0;
-	varint_u<1> outputvalid_cgen_out_0;
-	varint_u<1> outputstall_cgen_out_0;
-
-	// scalar inputs
-	varint_u<1> inputdata_AGen_Addr_En;
-	varint_u<33> inputdata_AGen_BlockSize_X;
-	varint_u<8> inputdata_AGen_CmdSize;
-	varint_u<31> inputdata_AGen_Offset_0;
-	varint_u<32> inputdata_AGen_Start_X_Addr;
-	varint_u<32> inputdata_AGen_Wrap_X;
-
-private:
-	maxcompilersim::DebugStreams *m_debug_output;
-	int m_node_number;
-
-	// integer state
-	varint_u<1> state1;
-	varint_u<31> state2;
-	varint_u<33> state4;
-	varint_u<32> state5;
-	varint_u<32> state6;
-	varint_u<8> state7;
-	varint_u<32> state8;
-	varint_u<32> state9;
-	varint_u<32> state10;
-	varint_u<1> state11;
-	varint_u<8> state12;
-
-	// enum state
-	varint_u<2> state3;
-};
-
-}
-}
-
-#endif // !defined(MANAGER_STATE_MACHINE_IMPL_addrgen_cmd_MemoryControllerPro0_inAT3_H)

tests/StreamFMA_MAX5C_DFE_SIM/scratch/software-sim/build/StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_inBT2.cpp

@@ -1,230 +0,0 @@
-#include "StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_inBT2.h"
-#include "SimException.h"
-
-namespace {
-
-	using maxcompilersim::varint_u;
-	using maxcompilersim::varint_s;
-
-	template<uint size>
-	varint_u<size> leading1detect(const varint_u<size> &x) {
-		varint_u<size> r;
-
-		for (uint i = 0; i < size; ++i) {
-			uint j = size - 1 - i;
-
-			if (x.get_bit(j)) {
-				r.set_bit(j, true);
-				break;
-			}
-		}
-
-		return r;
-	}
-
-	template<uint size>
-	varint_s<size> leading1detect(const varint_s<size> &x) {
-		varint_s<size> r;
-
-		for (uint i = 0; i < size; ++i) {
-			uint j = size - 1 - i;
-
-			if (x.get_bit(j)) {
-				r.set_bit(j, true);
-				break;
-			}
-		}
-
-		return r;
-	}
-
-	template<uint size>
-	varint_u<size> trailing1detect(const varint_u<size> &x) {
-		varint_u<size> r;
-
-		for (uint i = 0; i < size; ++i) {
-			if (x.get_bit(i)) {
-				r.set_bit(i, true);
-				break;
-			}
-		}
-
-		return r;
-	}
-
-	template<uint size>
-	varint_s<size> trailing1detect(const varint_s<size> &x) {
-		varint_s<size> r;
-
-		for (uint i = 0; i < size; ++i) {
-			if (x.get_bit(i)) {
-				r.set_bit(i, true);
-				break;
-			}
-		}
-
-		return r;
-	}
-
-	template<uint size, uint result_size>
-	varint_u<result_size> one_hot_decode(const varint_u<size> &x) {
-		varint_u<result_size> r;
-
-		for (uint i = 0; i < size; ++i) {
-			if (x.get_bit(i)) {
-				r.set_bits(0, result_size, i);
-				break;
-			}
-		}
-
-		return r;
-	}
-
-	template<uint size, uint result_size>
-	varint_u<result_size> one_hot_encode(const varint_u<size> &x) {
-		varint_u<result_size> r;
-
-		r.set_bit(x.toUInt64(), true);
-
-		return r;
-	}
-
-	template<uint size, uint result_size>
-	varint_s<result_size> one_hot_encode(const varint_s<size> &x) {
-		varint_s<result_size> r;
-
-		r.set_bit(x.toUInt64(), true);
-
-		return r;
-	}
-
-	template<uint size>
-	varint_u<size> reverse(const varint_u<size> &x) {
-		varint_u<size> r;
-
-		for (uint i = 0; i < size; ++i)
-			r.set_bit(i, x.get_bit(size - 1 - i));
-
-		return r;
-	}
-
-	template<uint size>
-	varint_s<size> reverse(const varint_s<size> &x) {
-		varint_s<size> r;
-
-		for (uint i = 0; i < size; ++i)
-			r.set_bit(i, x.get_bit(size - 1 - i));
-
-		return r;
-	}
-}
-maxcompilersim::state_machine::Manager_addrgen_cmd_MemoryControllerPro0_inBT2::Manager_addrgen_cmd_MemoryControllerPro0_inBT2(maxcompilersim::DebugStreams *debug_output, int node_number) :
-m_debug_output(debug_output),
-m_node_number(node_number),
-state8(0),
-state9(0),
-state10(0),
-state11(0),
-state12(0),
-state3(0)
-{ }
-
-
-
-void
-maxcompilersim::state_machine::Manager_addrgen_cmd_MemoryControllerPro0_inBT2::reset() {
-	state8 = 0;
-	state9 = 0;
-	state10 = 0;
-	state11 = 0;
-	state12 = 0;
-	state3 = 0;
-}
-
-
-
-void
-maxcompilersim::state_machine::Manager_addrgen_cmd_MemoryControllerPro0_inBT2::execute(const bool sm_not_flushing, const bool stall) {
-	varint_u<1> varint_sm_not_flushing(sm_not_flushing);
-	varint_u<1> next_state1(state1);
-	varint_u<31> next_state2(state2);
-	varint_u<33> next_state4(state4);
-	varint_u<32> next_state5(state5);
-	varint_u<32> next_state6(state6);
-	varint_u<8> next_state7(state7);
-	varint_u<32> next_state8(state8);
-	varint_u<32> next_state9(state9);
-	varint_u<32> next_state10(state10);
-	varint_u<1> next_state11(state11);
-	varint_u<8> next_state12(state12);
-	varint_u<2> next_state3(state3);
-	
-	varint_u<8> assignableVar1;
-	
-	next_state1 = inputdata_AGen_Addr_En;
-	next_state2 = inputdata_AGen_Offset_0;
-	next_state4 = inputdata_AGen_BlockSize_X;
-	next_state5 = inputdata_AGen_Wrap_X;
-	next_state6 = inputdata_AGen_Start_X_Addr;
-	next_state7 = inputdata_AGen_CmdSize;
-	outputdata_cgen_out_0 = varint_u<64>(0x0l);
-	outputvalid_cgen_out_0 = varint_u<1>(0x0l);
-	switch (static_cast<int>(state3)) {
-		case 0:
-			next_state8 = state6;
-			next_state9 = state6;
-			next_state10 = varint_u<32>(state4);
-			if (varint_u<1>(state1 != varint_u<1>(0x0l))) {
-				next_state3 = varint_u<2>(0x1l);
-			}
-			break;
-		case 1:
-			next_state9 = state8;
-			assignableVar1 = state7;
-			if (varint_u<1>(state10 < varint_u<32>(assignableVar1))) {
-				assignableVar1 = varint_u<8>(state10);
-			}
-			if (varint_u<1>((state5 - state8) < varint_u<32>(assignableVar1)) & varint_u<1>((state5 - state8) < state10)) {
-				assignableVar1 = varint_u<8>(state5 - state8);
-				next_state8 = varint_u<32>(0x0l);
-			} else {
-				next_state8 = state8 + varint_u<32>(assignableVar1);
-				if (varint_u<1>(state8 >= varint_u<32>(0x80000000l))) {
-					next_state8 = varint_u<32>(0x7fffffffl) & state8;
-				}
-			}
-			next_state10 = state10 - varint_u<32>(assignableVar1);
-			next_state12 = assignableVar1;
-			next_state11 = varint_u<1>((state10 - varint_u<32>(assignableVar1)) == varint_u<32>(0x0l));
-			next_state3 = varint_u<2>(0x2l);
-			break;
-		case 2:
-			if ((~(varint_u<1>(0x0l) | outputstall_cgen_out_0))) {
-				outputdata_cgen_out_0 = varint_u<1>(state11).cat(varint_u<15>(0x1l)).cat(varint_u<1>(varint_u<1>(0x0l))).cat(varint_u<7>(varint_u<8>(0x1l))).cat(varint_u<8>(state12)).cat(varint_u<1>(0x0l)).cat(varint_u<31>((state9 + varint_u<32>(state2))));
-				outputvalid_cgen_out_0 = (state1).slice<0, 1>();
-				if (state11) {
-					next_state3 = varint_u<2>(0x3l);
-				} else {
-					next_state3 = varint_u<2>(0x1l);
-				}
-			}
-			break;
-	}
-	
-	// update states
-	if (!stall) {
-		state1 = next_state1;
-		state2 = next_state2;
-		state4 = next_state4;
-		state5 = next_state5;
-		state6 = next_state6;
-		state7 = next_state7;
-		state8 = next_state8;
-		state9 = next_state9;
-		state10 = next_state10;
-		state11 = next_state11;
-		state12 = next_state12;
-		state3 = next_state3;
-	}
-	
-}

tests/StreamFMA_MAX5C_DFE_SIM/scratch/software-sim/build/StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_inBT2.h

@@ -1,54 +0,0 @@
-#ifndef MANAGER_STATE_MACHINE_IMPL_addrgen_cmd_MemoryControllerPro0_inBT2_H
-#define MANAGER_STATE_MACHINE_IMPL_addrgen_cmd_MemoryControllerPro0_inBT2_H
-
-#include "HWTypes.h"
-#include "Debuggable.h"
-
-namespace maxcompilersim {
-namespace state_machine {
-
-class Manager_addrgen_cmd_MemoryControllerPro0_inBT2 {
-public:
-	Manager_addrgen_cmd_MemoryControllerPro0_inBT2(maxcompilersim::DebugStreams *debug_output, int node_number);
-	void reset();
-	void execute() {execute(true, false);}
-	void execute(bool sm_not_flushing, bool stall);
-
-	// push outputs
-	varint_u<64> outputdata_cgen_out_0;
-	varint_u<1> outputvalid_cgen_out_0;
-	varint_u<1> outputstall_cgen_out_0;
-
-	// scalar inputs
-	varint_u<1> inputdata_AGen_Addr_En;
-	varint_u<33> inputdata_AGen_BlockSize_X;
-	varint_u<8> inputdata_AGen_CmdSize;
-	varint_u<31> inputdata_AGen_Offset_0;
-	varint_u<32> inputdata_AGen_Start_X_Addr;
-	varint_u<32> inputdata_AGen_Wrap_X;
-
-private:
-	maxcompilersim::DebugStreams *m_debug_output;
-	int m_node_number;
-
-	// integer state
-	varint_u<1> state1;
-	varint_u<31> state2;
-	varint_u<33> state4;
-	varint_u<32> state5;
-	varint_u<32> state6;
-	varint_u<8> state7;
-	varint_u<32> state8;
-	varint_u<32> state9;
-	varint_u<32> state10;
-	varint_u<1> state11;
-	varint_u<8> state12;
-
-	// enum state
-	varint_u<2> state3;
-};
-
-}
-}
-
-#endif // !defined(MANAGER_STATE_MACHINE_IMPL_addrgen_cmd_MemoryControllerPro0_inBT2_H)

tests/StreamFMA_MAX5C_DFE_SIM/scratch/software-sim/build/StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_inBT3.cpp

@@ -1,230 +0,0 @@
-#include "StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_inBT3.h"
-#include "SimException.h"
-
-namespace {
-
-	using maxcompilersim::varint_u;
-	using maxcompilersim::varint_s;
-
-	template<uint size>
-	varint_u<size> leading1detect(const varint_u<size> &x) {
-		varint_u<size> r;
-
-		for (uint i = 0; i < size; ++i) {
-			uint j = size - 1 - i;
-
-			if (x.get_bit(j)) {
-				r.set_bit(j, true);
-				break;
-			}
-		}
-
-		return r;
-	}
-
-	template<uint size>
-	varint_s<size> leading1detect(const varint_s<size> &x) {
-		varint_s<size> r;
-
-		for (uint i = 0; i < size; ++i) {
-			uint j = size - 1 - i;
-
-			if (x.get_bit(j)) {
-				r.set_bit(j, true);
-				break;
-			}
-		}
-
-		return r;
-	}
-
-	template<uint size>
-	varint_u<size> trailing1detect(const varint_u<size> &x) {
-		varint_u<size> r;
-
-		for (uint i = 0; i < size; ++i) {
-			if (x.get_bit(i)) {
-				r.set_bit(i, true);
-				break;
-			}
-		}
-
-		return r;
-	}
-
-	template<uint size>
-	varint_s<size> trailing1detect(const varint_s<size> &x) {
-		varint_s<size> r;
-
-		for (uint i = 0; i < size; ++i) {
-			if (x.get_bit(i)) {
-				r.set_bit(i, true);
-				break;
-			}
-		}
-
-		return r;
-	}
-
-	template<uint size, uint result_size>
-	varint_u<result_size> one_hot_decode(const varint_u<size> &x) {
-		varint_u<result_size> r;
-
-		for (uint i = 0; i < size; ++i) {
-			if (x.get_bit(i)) {
-				r.set_bits(0, result_size, i);
-				break;
-			}
-		}
-
-		return r;
-	}
-
-	template<uint size, uint result_size>
-	varint_u<result_size> one_hot_encode(const varint_u<size> &x) {
-		varint_u<result_size> r;
-
-		r.set_bit(x.toUInt64(), true);
-
-		return r;
-	}
-
-	template<uint size, uint result_size>
-	varint_s<result_size> one_hot_encode(const varint_s<size> &x) {
-		varint_s<result_size> r;
-
-		r.set_bit(x.toUInt64(), true);
-
-		return r;
-	}
-
-	template<uint size>
-	varint_u<size> reverse(const varint_u<size> &x) {
-		varint_u<size> r;
-
-		for (uint i = 0; i < size; ++i)
-			r.set_bit(i, x.get_bit(size - 1 - i));
-
-		return r;
-	}
-
-	template<uint size>
-	varint_s<size> reverse(const varint_s<size> &x) {
-		varint_s<size> r;
-
-		for (uint i = 0; i < size; ++i)
-			r.set_bit(i, x.get_bit(size - 1 - i));
-
-		return r;
-	}
-}
-maxcompilersim::state_machine::Manager_addrgen_cmd_MemoryControllerPro0_inBT3::Manager_addrgen_cmd_MemoryControllerPro0_inBT3(maxcompilersim::DebugStreams *debug_output, int node_number) :
-m_debug_output(debug_output),
-m_node_number(node_number),
-state8(0),
-state9(0),
-state10(0),
-state11(0),
-state12(0),
-state3(0)
-{ }
-
-
-
-void
-maxcompilersim::state_machine::Manager_addrgen_cmd_MemoryControllerPro0_inBT3::reset() {
-	state8 = 0;
-	state9 = 0;
-	state10 = 0;
-	state11 = 0;
-	state12 = 0;
-	state3 = 0;
-}
-
-
-
-void
-maxcompilersim::state_machine::Manager_addrgen_cmd_MemoryControllerPro0_inBT3::execute(const bool sm_not_flushing, const bool stall) {
-	varint_u<1> varint_sm_not_flushing(sm_not_flushing);
-	varint_u<1> next_state1(state1);
-	varint_u<31> next_state2(state2);
-	varint_u<33> next_state4(state4);
-	varint_u<32> next_state5(state5);
-	varint_u<32> next_state6(state6);
-	varint_u<8> next_state7(state7);
-	varint_u<32> next_state8(state8);
-	varint_u<32> next_state9(state9);
-	varint_u<32> next_state10(state10);
-	varint_u<1> next_state11(state11);
-	varint_u<8> next_state12(state12);
-	varint_u<2> next_state3(state3);
-	
-	varint_u<8> assignableVar1;
-	
-	next_state1 = inputdata_AGen_Addr_En;
-	next_state2 = inputdata_AGen_Offset_0;
-	next_state4 = inputdata_AGen_BlockSize_X;
-	next_state5 = inputdata_AGen_Wrap_X;
-	next_state6 = inputdata_AGen_Start_X_Addr;
-	next_state7 = inputdata_AGen_CmdSize;
-	outputdata_cgen_out_0 = varint_u<64>(0x0l);
-	outputvalid_cgen_out_0 = varint_u<1>(0x0l);
-	switch (static_cast<int>(state3)) {
-		case 0:
-			next_state8 = state6;
-			next_state9 = state6;
-			next_state10 = varint_u<32>(state4);
-			if (varint_u<1>(state1 != varint_u<1>(0x0l))) {
-				next_state3 = varint_u<2>(0x1l);
-			}
-			break;
-		case 1:
-			next_state9 = state8;
-			assignableVar1 = state7;
-			if (varint_u<1>(state10 < varint_u<32>(assignableVar1))) {
-				assignableVar1 = varint_u<8>(state10);
-			}
-			if (varint_u<1>((state5 - state8) < varint_u<32>(assignableVar1)) & varint_u<1>((state5 - state8) < state10)) {
-				assignableVar1 = varint_u<8>(state5 - state8);
-				next_state8 = varint_u<32>(0x0l);
-			} else {
-				next_state8 = state8 + varint_u<32>(assignableVar1);
-				if (varint_u<1>(state8 >= varint_u<32>(0x80000000l))) {
-					next_state8 = varint_u<32>(0x7fffffffl) & state8;
-				}
-			}
-			next_state10 = state10 - varint_u<32>(assignableVar1);
-			next_state12 = assignableVar1;
-			next_state11 = varint_u<1>((state10 - varint_u<32>(assignableVar1)) == varint_u<32>(0x0l));
-			next_state3 = varint_u<2>(0x2l);
-			break;
-		case 2:
-			if ((~(varint_u<1>(0x0l) | outputstall_cgen_out_0))) {
-				outputdata_cgen_out_0 = varint_u<1>(state11).cat(varint_u<15>(0x1l)).cat(varint_u<1>(varint_u<1>(0x0l))).cat(varint_u<7>(varint_u<8>(0x1l))).cat(varint_u<8>(state12)).cat(varint_u<1>(0x0l)).cat(varint_u<31>((state9 + varint_u<32>(state2))));
-				outputvalid_cgen_out_0 = (state1).slice<0, 1>();
-				if (state11) {
-					next_state3 = varint_u<2>(0x3l);
-				} else {
-					next_state3 = varint_u<2>(0x1l);
-				}
-			}
-			break;
-	}
-	
-	// update states
-	if (!stall) {
-		state1 = next_state1;
-		state2 = next_state2;
-		state4 = next_state4;
-		state5 = next_state5;
-		state6 = next_state6;
-		state7 = next_state7;
-		state8 = next_state8;
-		state9 = next_state9;
-		state10 = next_state10;
-		state11 = next_state11;
-		state12 = next_state12;
-		state3 = next_state3;
-	}
-	
-}

tests/StreamFMA_MAX5C_DFE_SIM/scratch/software-sim/build/StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_inBT3.h

@@ -1,54 +0,0 @@
-#ifndef MANAGER_STATE_MACHINE_IMPL_addrgen_cmd_MemoryControllerPro0_inBT3_H
-#define MANAGER_STATE_MACHINE_IMPL_addrgen_cmd_MemoryControllerPro0_inBT3_H
-
-#include "HWTypes.h"
-#include "Debuggable.h"
-
-namespace maxcompilersim {
-namespace state_machine {
-
-class Manager_addrgen_cmd_MemoryControllerPro0_inBT3 {
-public:
-	Manager_addrgen_cmd_MemoryControllerPro0_inBT3(maxcompilersim::DebugStreams *debug_output, int node_number);
-	void reset();
-	void execute() {execute(true, false);}
-	void execute(bool sm_not_flushing, bool stall);
-
-	// push outputs
-	varint_u<64> outputdata_cgen_out_0;
-	varint_u<1> outputvalid_cgen_out_0;
-	varint_u<1> outputstall_cgen_out_0;
-
-	// scalar inputs
-	varint_u<1> inputdata_AGen_Addr_En;
-	varint_u<33> inputdata_AGen_BlockSize_X;
-	varint_u<8> inputdata_AGen_CmdSize;
-	varint_u<31> inputdata_AGen_Offset_0;
-	varint_u<32> inputdata_AGen_Start_X_Addr;
-	varint_u<32> inputdata_AGen_Wrap_X;
-
-private:
-	maxcompilersim::DebugStreams *m_debug_output;
-	int m_node_number;
-
-	// integer state
-	varint_u<1> state1;
-	varint_u<31> state2;
-	varint_u<33> state4;
-	varint_u<32> state5;
-	varint_u<32> state6;
-	varint_u<8> state7;
-	varint_u<32> state8;
-	varint_u<32> state9;
-	varint_u<32> state10;
-	varint_u<1> state11;
-	varint_u<8> state12;
-
-	// enum state
-	varint_u<2> state3;
-};
-
-}
-}
-
-#endif // !defined(MANAGER_STATE_MACHINE_IMPL_addrgen_cmd_MemoryControllerPro0_inBT3_H)

tests/StreamFMA_MAX5C_DFE_SIM/scratch/software-sim/build/StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_oDataT1.cpp

@@ -1,230 +0,0 @@
-#include "StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_oDataT1.h"
-#include "SimException.h"
-
-namespace {
-
-	using maxcompilersim::varint_u;
-	using maxcompilersim::varint_s;
-
-	template<uint size>
-	varint_u<size> leading1detect(const varint_u<size> &x) {
-		varint_u<size> r;
-
-		for (uint i = 0; i < size; ++i) {
-			uint j = size - 1 - i;
-
-			if (x.get_bit(j)) {
-				r.set_bit(j, true);
-				break;
-			}
-		}
-
-		return r;
-	}
-
-	template<uint size>
-	varint_s<size> leading1detect(const varint_s<size> &x) {
-		varint_s<size> r;
-
-		for (uint i = 0; i < size; ++i) {
-			uint j = size - 1 - i;
-
-			if (x.get_bit(j)) {
-				r.set_bit(j, true);
-				break;
-			}
-		}
-
-		return r;
-	}
-
-	template<uint size>
-	varint_u<size> trailing1detect(const varint_u<size> &x) {
-		varint_u<size> r;
-
-		for (uint i = 0; i < size; ++i) {
-			if (x.get_bit(i)) {
-				r.set_bit(i, true);
-				break;
-			}
-		}
-
-		return r;
-	}
-
-	template<uint size>
-	varint_s<size> trailing1detect(const varint_s<size> &x) {
-		varint_s<size> r;
-
-		for (uint i = 0; i < size; ++i) {
-			if (x.get_bit(i)) {
-				r.set_bit(i, true);
-				break;
-			}
-		}
-
-		return r;
-	}
-
-	template<uint size, uint result_size>
-	varint_u<result_size> one_hot_decode(const varint_u<size> &x) {
-		varint_u<result_size> r;
-
-		for (uint i = 0; i < size; ++i) {
-			if (x.get_bit(i)) {
-				r.set_bits(0, result_size, i);
-				break;
-			}
-		}
-
-		return r;
-	}
-
-	template<uint size, uint result_size>
-	varint_u<result_size> one_hot_encode(const varint_u<size> &x) {
-		varint_u<result_size> r;
-
-		r.set_bit(x.toUInt64(), true);
-
-		return r;
-	}
-
-	template<uint size, uint result_size>
-	varint_s<result_size> one_hot_encode(const varint_s<size> &x) {
-		varint_s<result_size> r;
-
-		r.set_bit(x.toUInt64(), true);
-
-		return r;
-	}
-
-	template<uint size>
-	varint_u<size> reverse(const varint_u<size> &x) {
-		varint_u<size> r;
-
-		for (uint i = 0; i < size; ++i)
-			r.set_bit(i, x.get_bit(size - 1 - i));
-
-		return r;
-	}
-
-	template<uint size>
-	varint_s<size> reverse(const varint_s<size> &x) {
-		varint_s<size> r;
-
-		for (uint i = 0; i < size; ++i)
-			r.set_bit(i, x.get_bit(size - 1 - i));
-
-		return r;
-	}
-}
-maxcompilersim::state_machine::Manager_addrgen_cmd_MemoryControllerPro0_oDataT1::Manager_addrgen_cmd_MemoryControllerPro0_oDataT1(maxcompilersim::DebugStreams *debug_output, int node_number) :
-m_debug_output(debug_output),
-m_node_number(node_number),
-state8(0),
-state9(0),
-state10(0),
-state11(0),
-state12(0),
-state3(0)
-{ }
-
-
-
-void
-maxcompilersim::state_machine::Manager_addrgen_cmd_MemoryControllerPro0_oDataT1::reset() {
-	state8 = 0;
-	state9 = 0;
-	state10 = 0;
-	state11 = 0;
-	state12 = 0;
-	state3 = 0;
-}
-
-
-
-void
-maxcompilersim::state_machine::Manager_addrgen_cmd_MemoryControllerPro0_oDataT1::execute(const bool sm_not_flushing, const bool stall) {
-	varint_u<1> varint_sm_not_flushing(sm_not_flushing);
-	varint_u<1> next_state1(state1);
-	varint_u<31> next_state2(state2);
-	varint_u<33> next_state4(state4);
-	varint_u<32> next_state5(state5);
-	varint_u<32> next_state6(state6);
-	varint_u<8> next_state7(state7);
-	varint_u<32> next_state8(state8);
-	varint_u<32> next_state9(state9);
-	varint_u<32> next_state10(state10);
-	varint_u<1> next_state11(state11);
-	varint_u<8> next_state12(state12);
-	varint_u<2> next_state3(state3);
-	
-	varint_u<8> assignableVar1;
-	
-	next_state1 = inputdata_AGen_Addr_En;
-	next_state2 = inputdata_AGen_Offset_0;
-	next_state4 = inputdata_AGen_BlockSize_X;
-	next_state5 = inputdata_AGen_Wrap_X;
-	next_state6 = inputdata_AGen_Start_X_Addr;
-	next_state7 = inputdata_AGen_CmdSize;
-	outputdata_cgen_out_0 = varint_u<64>(0x0l);
-	outputvalid_cgen_out_0 = varint_u<1>(0x0l);
-	switch (static_cast<int>(state3)) {
-		case 0:
-			next_state8 = state6;
-			next_state9 = state6;
-			next_state10 = varint_u<32>(state4);
-			if (varint_u<1>(state1 != varint_u<1>(0x0l))) {
-				next_state3 = varint_u<2>(0x1l);
-			}
-			break;
-		case 1:
-			next_state9 = state8;
-			assignableVar1 = state7;
-			if (varint_u<1>(state10 < varint_u<32>(assignableVar1))) {
-				assignableVar1 = varint_u<8>(state10);
-			}
-			if (varint_u<1>((state5 - state8) < varint_u<32>(assignableVar1)) & varint_u<1>((state5 - state8) < state10)) {
-				assignableVar1 = varint_u<8>(state5 - state8);
-				next_state8 = varint_u<32>(0x0l);
-			} else {
-				next_state8 = state8 + varint_u<32>(assignableVar1);
-				if (varint_u<1>(state8 >= varint_u<32>(0x80000000l))) {
-					next_state8 = varint_u<32>(0x7fffffffl) & state8;
-				}
-			}
-			next_state10 = state10 - varint_u<32>(assignableVar1);
-			next_state12 = assignableVar1;
-			next_state11 = varint_u<1>((state10 - varint_u<32>(assignableVar1)) == varint_u<32>(0x0l));
-			next_state3 = varint_u<2>(0x2l);
-			break;
-		case 2:
-			if ((~(varint_u<1>(0x0l) | outputstall_cgen_out_0))) {
-				outputdata_cgen_out_0 = varint_u<1>(state11).cat(varint_u<15>(0x1l)).cat(varint_u<1>(varint_u<1>(0x0l))).cat(varint_u<7>(varint_u<8>(0x1l))).cat(varint_u<8>(state12)).cat(varint_u<1>(0x0l)).cat(varint_u<31>((state9 + varint_u<32>(state2))));
-				outputvalid_cgen_out_0 = (state1).slice<0, 1>();
-				if (state11) {
-					next_state3 = varint_u<2>(0x3l);
-				} else {
-					next_state3 = varint_u<2>(0x1l);
-				}
-			}
-			break;
-	}
-	
-	// update states
-	if (!stall) {
-		state1 = next_state1;
-		state2 = next_state2;
-		state4 = next_state4;
-		state5 = next_state5;
-		state6 = next_state6;
-		state7 = next_state7;
-		state8 = next_state8;
-		state9 = next_state9;
-		state10 = next_state10;
-		state11 = next_state11;
-		state12 = next_state12;
-		state3 = next_state3;
-	}
-	
-}

tests/StreamFMA_MAX5C_DFE_SIM/scratch/software-sim/build/StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_oDataT1.h

@@ -1,54 +0,0 @@
-#ifndef MANAGER_STATE_MACHINE_IMPL_addrgen_cmd_MemoryControllerPro0_oDataT1_H
-#define MANAGER_STATE_MACHINE_IMPL_addrgen_cmd_MemoryControllerPro0_oDataT1_H
-
-#include "HWTypes.h"
-#include "Debuggable.h"
-
-namespace maxcompilersim {
-namespace state_machine {
-
-class Manager_addrgen_cmd_MemoryControllerPro0_oDataT1 {
-public:
-	Manager_addrgen_cmd_MemoryControllerPro0_oDataT1(maxcompilersim::DebugStreams *debug_output, int node_number);
-	void reset();
-	void execute() {execute(true, false);}
-	void execute(bool sm_not_flushing, bool stall);
-
-	// push outputs
-	varint_u<64> outputdata_cgen_out_0;
-	varint_u<1> outputvalid_cgen_out_0;
-	varint_u<1> outputstall_cgen_out_0;
-
-	// scalar inputs
-	varint_u<1> inputdata_AGen_Addr_En;
-	varint_u<33> inputdata_AGen_BlockSize_X;
-	varint_u<8> inputdata_AGen_CmdSize;
-	varint_u<31> inputdata_AGen_Offset_0;
-	varint_u<32> inputdata_AGen_Start_X_Addr;
-	varint_u<32> inputdata_AGen_Wrap_X;
-
-private:
-	maxcompilersim::DebugStreams *m_debug_output;
-	int m_node_number;
-
-	// integer state
-	varint_u<1> state1;
-	varint_u<31> state2;
-	varint_u<33> state4;
-	varint_u<32> state5;
-	varint_u<32> state6;
-	varint_u<8> state7;
-	varint_u<32> state8;
-	varint_u<32> state9;
-	varint_u<32> state10;
-	varint_u<1> state11;
-	varint_u<8> state12;
-
-	// enum state
-	varint_u<2> state3;
-};
-
-}
-}
-
-#endif // !defined(MANAGER_STATE_MACHINE_IMPL_addrgen_cmd_MemoryControllerPro0_oDataT1_H)

tests/StreamFMA_MAX5C_DFE_SIM/scratch/software-sim/build/StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_oDataT2.cpp

@@ -1,230 +0,0 @@
-#include "StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_oDataT2.h"
-#include "SimException.h"
-
-namespace {
-
-	using maxcompilersim::varint_u;
-	using maxcompilersim::varint_s;
-
-	template<uint size>
-	varint_u<size> leading1detect(const varint_u<size> &x) {
-		varint_u<size> r;
-
-		for (uint i = 0; i < size; ++i) {
-			uint j = size - 1 - i;
-
-			if (x.get_bit(j)) {
-				r.set_bit(j, true);
-				break;
-			}
-		}
-
-		return r;
-	}
-
-	template<uint size>
-	varint_s<size> leading1detect(const varint_s<size> &x) {
-		varint_s<size> r;
-
-		for (uint i = 0; i < size; ++i) {
-			uint j = size - 1 - i;
-
-			if (x.get_bit(j)) {
-				r.set_bit(j, true);
-				break;
-			}
-		}
-
-		return r;
-	}
-
-	template<uint size>
-	varint_u<size> trailing1detect(const varint_u<size> &x) {
-		varint_u<size> r;
-
-		for (uint i = 0; i < size; ++i) {
-			if (x.get_bit(i)) {
-				r.set_bit(i, true);
-				break;
-			}
-		}
-
-		return r;
-	}
-
-	template<uint size>
-	varint_s<size> trailing1detect(const varint_s<size> &x) {
-		varint_s<size> r;
-
-		for (uint i = 0; i < size; ++i) {
-			if (x.get_bit(i)) {
-				r.set_bit(i, true);
-				break;
-			}
-		}
-
-		return r;
-	}
-
-	template<uint size, uint result_size>
-	varint_u<result_size> one_hot_decode(const varint_u<size> &x) {
-		varint_u<result_size> r;
-
-		for (uint i = 0; i < size; ++i) {
-			if (x.get_bit(i)) {
-				r.set_bits(0, result_size, i);
-				break;
-			}
-		}
-
-		return r;
-	}
-
-	template<uint size, uint result_size>
-	varint_u<result_size> one_hot_encode(const varint_u<size> &x) {
-		varint_u<result_size> r;
-
-		r.set_bit(x.toUInt64(), true);
-
-		return r;
-	}
-
-	template<uint size, uint result_size>
-	varint_s<result_size> one_hot_encode(const varint_s<size> &x) {
-		varint_s<result_size> r;
-
-		r.set_bit(x.toUInt64(), true);
-
-		return r;
-	}
-
-	template<uint size>
-	varint_u<size> reverse(const varint_u<size> &x) {
-		varint_u<size> r;
-
-		for (uint i = 0; i < size; ++i)
-			r.set_bit(i, x.get_bit(size - 1 - i));
-
-		return r;
-	}
-
-	template<uint size>
-	varint_s<size> reverse(const varint_s<size> &x) {
-		varint_s<size> r;
-
-		for (uint i = 0; i < size; ++i)
-			r.set_bit(i, x.get_bit(size - 1 - i));
-
-		return r;
-	}
-}
-maxcompilersim::state_machine::Manager_addrgen_cmd_MemoryControllerPro0_oDataT2::Manager_addrgen_cmd_MemoryControllerPro0_oDataT2(maxcompilersim::DebugStreams *debug_output, int node_number) :
-m_debug_output(debug_output),
-m_node_number(node_number),
-state8(0),
-state9(0),
-state10(0),
-state11(0),
-state12(0),
-state3(0)
-{ }
-
-
-
-void
-maxcompilersim::state_machine::Manager_addrgen_cmd_MemoryControllerPro0_oDataT2::reset() {
-	state8 = 0;
-	state9 = 0;
-	state10 = 0;
-	state11 = 0;
-	state12 = 0;
-	state3 = 0;
-}
-
-
-
-void
-maxcompilersim::state_machine::Manager_addrgen_cmd_MemoryControllerPro0_oDataT2::execute(const bool sm_not_flushing, const bool stall) {
-	varint_u<1> varint_sm_not_flushing(sm_not_flushing);
-	varint_u<1> next_state1(state1);
-	varint_u<31> next_state2(state2);
-	varint_u<33> next_state4(state4);
-	varint_u<32> next_state5(state5);
-	varint_u<32> next_state6(state6);
-	varint_u<8> next_state7(state7);
-	varint_u<32> next_state8(state8);
-	varint_u<32> next_state9(state9);
-	varint_u<32> next_state10(state10);
-	varint_u<1> next_state11(state11);
-	varint_u<8> next_state12(state12);
-	varint_u<2> next_state3(state3);
-	
-	varint_u<8> assignableVar1;
-	
-	next_state1 = inputdata_AGen_Addr_En;
-	next_state2 = inputdata_AGen_Offset_0;
-	next_state4 = inputdata_AGen_BlockSize_X;
-	next_state5 = inputdata_AGen_Wrap_X;
-	next_state6 = inputdata_AGen_Start_X_Addr;
-	next_state7 = inputdata_AGen_CmdSize;
-	outputdata_cgen_out_0 = varint_u<64>(0x0l);
-	outputvalid_cgen_out_0 = varint_u<1>(0x0l);
-	switch (static_cast<int>(state3)) {
-		case 0:
-			next_state8 = state6;
-			next_state9 = state6;
-			next_state10 = varint_u<32>(state4);
-			if (varint_u<1>(state1 != varint_u<1>(0x0l))) {
-				next_state3 = varint_u<2>(0x1l);
-			}
-			break;
-		case 1:
-			next_state9 = state8;
-			assignableVar1 = state7;
-			if (varint_u<1>(state10 < varint_u<32>(assignableVar1))) {
-				assignableVar1 = varint_u<8>(state10);
-			}
-			if (varint_u<1>((state5 - state8) < varint_u<32>(assignableVar1)) & varint_u<1>((state5 - state8) < state10)) {
-				assignableVar1 = varint_u<8>(state5 - state8);
-				next_state8 = varint_u<32>(0x0l);
-			} else {
-				next_state8 = state8 + varint_u<32>(assignableVar1);
-				if (varint_u<1>(state8 >= varint_u<32>(0x80000000l))) {
-					next_state8 = varint_u<32>(0x7fffffffl) & state8;
-				}
-			}
-			next_state10 = state10 - varint_u<32>(assignableVar1);
-			next_state12 = assignableVar1;
-			next_state11 = varint_u<1>((state10 - varint_u<32>(assignableVar1)) == varint_u<32>(0x0l));
-			next_state3 = varint_u<2>(0x2l);
-			break;
-		case 2:
-			if ((~(varint_u<1>(0x0l) | outputstall_cgen_out_0))) {
-				outputdata_cgen_out_0 = varint_u<1>(state11).cat(varint_u<15>(0x1l)).cat(varint_u<1>(varint_u<1>(0x0l))).cat(varint_u<7>(varint_u<8>(0x1l))).cat(varint_u<8>(state12)).cat(varint_u<1>(0x0l)).cat(varint_u<31>((state9 + varint_u<32>(state2))));
-				outputvalid_cgen_out_0 = (state1).slice<0, 1>();
-				if (state11) {
-					next_state3 = varint_u<2>(0x3l);
-				} else {
-					next_state3 = varint_u<2>(0x1l);
-				}
-			}
-			break;
-	}
-	
-	// update states
-	if (!stall) {
-		state1 = next_state1;
-		state2 = next_state2;
-		state4 = next_state4;
-		state5 = next_state5;
-		state6 = next_state6;
-		state7 = next_state7;
-		state8 = next_state8;
-		state9 = next_state9;
-		state10 = next_state10;
-		state11 = next_state11;
-		state12 = next_state12;
-		state3 = next_state3;
-	}
-	
-}

tests/StreamFMA_MAX5C_DFE_SIM/scratch/software-sim/build/StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_oDataT2.h

@@ -1,54 +0,0 @@
-#ifndef MANAGER_STATE_MACHINE_IMPL_addrgen_cmd_MemoryControllerPro0_oDataT2_H
-#define MANAGER_STATE_MACHINE_IMPL_addrgen_cmd_MemoryControllerPro0_oDataT2_H
-
-#include "HWTypes.h"
-#include "Debuggable.h"
-
-namespace maxcompilersim {
-namespace state_machine {
-
-class Manager_addrgen_cmd_MemoryControllerPro0_oDataT2 {
-public:
-	Manager_addrgen_cmd_MemoryControllerPro0_oDataT2(maxcompilersim::DebugStreams *debug_output, int node_number);
-	void reset();
-	void execute() {execute(true, false);}
-	void execute(bool sm_not_flushing, bool stall);
-
-	// push outputs
-	varint_u<64> outputdata_cgen_out_0;
-	varint_u<1> outputvalid_cgen_out_0;
-	varint_u<1> outputstall_cgen_out_0;
-
-	// scalar inputs
-	varint_u<1> inputdata_AGen_Addr_En;
-	varint_u<33> inputdata_AGen_BlockSize_X;
-	varint_u<8> inputdata_AGen_CmdSize;
-	varint_u<31> inputdata_AGen_Offset_0;
-	varint_u<32> inputdata_AGen_Start_X_Addr;
-	varint_u<32> inputdata_AGen_Wrap_X;
-
-private:
-	maxcompilersim::DebugStreams *m_debug_output;
-	int m_node_number;
-
-	// integer state
-	varint_u<1> state1;
-	varint_u<31> state2;
-	varint_u<33> state4;
-	varint_u<32> state5;
-	varint_u<32> state6;
-	varint_u<8> state7;
-	varint_u<32> state8;
-	varint_u<32> state9;
-	varint_u<32> state10;
-	varint_u<1> state11;
-	varint_u<8> state12;
-
-	// enum state
-	varint_u<2> state3;
-};
-
-}
-}
-
-#endif // !defined(MANAGER_STATE_MACHINE_IMPL_addrgen_cmd_MemoryControllerPro0_oDataT2_H)

tests/StreamFMA_MAX5C_DFE_SIM/scratch/software-sim/build/StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_oDataT3.cpp

@@ -1,230 +0,0 @@
-#include "StateMachine_impl_M_addrgen_cmd_MemoryControllerPro0_oDataT3.h"
-#include "SimException.h"
-
-namespace {
-
-	using maxcompilersim::varint_u;
-	using maxcompilersim::varint_s;
-
-	template<uint size>
-	varint_u<size> leading1detect(const varint_u<size> &x) {
-		varint_u<size> r;
-
-		for (uint i = 0; i < size; ++i) {
-			uint j = size - 1 - i;
-
-			if (x.get_bit(j)) {
-				r.set_bit(j, true);
-				break;
-			}
-		}
-
-		return r;
-	}
-
-	template<uint size>
-	varint_s<size> leading1detect(const varint_s<size> &x) {
-		varint_s<size> r;
-
-		for (uint i = 0; i < size; ++i) {
-			uint j = size - 1 - i;
-
-			if (x.get_bit(j)) {
-				r.set_bit(j, true);
-				break;
-			}
-		}
-
-		return r;
-	}
-
-	template<uint size>
-	varint_u<size> trailing1detect(const varint_u<size> &x) {
-		varint_u<size> r;
-
-		for (uint i = 0; i < size; ++i) {
-			if (x.get_bit(i)) {
-				r.set_bit(i, true);
-				break;
-			}
-		}
-
-		return r;
-	}
-
-	template<uint size>
-	varint_s<size> trailing1detect(const varint_s<size> &x) {
-		varint_s<size> r;
-
-		for (uint i = 0; i < size; ++i) {
-			if (x.get_bit(i)) {
-				r.set_bit(i, true);
-				break;
-			}
-		}
-
-		return r;
-	}
-
-	template<uint size, uint result_size>
-	varint_u<result_size> one_hot_decode(const varint_u<size> &x) {
-		varint_u<result_size> r;
-
-		for (uint i = 0; i < size; ++i) {
-			if (x.get_bit(i)) {
-				r.set_bits(0, result_size, i);
-				break;
-			}
-		}
-
-		return r;
-	}
-
-	template<uint size, uint result_size>
-	varint_u<result_size> one_hot_encode(const varint_u<size> &x) {
-		varint_u<result_size> r;
-
-		r.set_bit(x.toUInt64(), true);
-
-		return r;
-	}
-
-	template<uint size, uint result_size>
-	varint_s<result_size> one_hot_encode(const varint_s<size> &x) {
-		varint_s<result_size> r;
-
-		r.set_bit(x.toUInt64(), true);
-
-		return r;
-	}
-
-	template<uint size>
-	varint_u<size> reverse(const varint_u<size> &x) {
-		varint_u<size> r;
-
-		for (uint i = 0; i < size; ++i)
-			r.set_bit(i, x.get_bit(size - 1 - i));
-
-		return r;
-	}
-
-	template<uint size>
-	varint_s<size> reverse(const varint_s<size> &x) {
-		varint_s<size> r;
-
-		for (uint i = 0; i < size; ++i)
-			r.set_bit(i, x.get_bit(size - 1 - i));
-
-		return r;
-	}
-}
-maxcompilersim::state_machine::Manager_addrgen_cmd_MemoryControllerPro0_oDataT3::Manager_addrgen_cmd_MemoryControllerPro0_oDataT3(maxcompilersim::DebugStreams *debug_output, int node_number) :
-m_debug_output(debug_output),
-m_node_number(node_number),
-state8(0),
-state9(0),
-state10(0),
-state11(0),
-state12(0),
-state3(0)
-{ }
-
-
-
-void
-maxcompilersim::state_machine::Manager_addrgen_cmd_MemoryControllerPro0_oDataT3::reset() {
-	state8 = 0;
-	state9 = 0;
-	state10 = 0;
-	state11 = 0;
-	state12 = 0;
-	state3 = 0;
-}
-
-
-
-void
-maxcompilersim::state_machine::Manager_addrgen_cmd_MemoryControllerPro0_oDataT3::execute(const bool sm_not_flushing, const bool stall) {
-	varint_u<1> varint_sm_not_flushing(sm_not_flushing);
-	varint_u<1> next_state1(state1);
-	varint_u<31> next_state2(state2);
-	varint_u<33> next_state4(state4);
-	varint_u<32> next_state5(state5);
-	varint_u<32> next_state6(state6);
-	varint_u<8> next_state7(state7);
-	varint_u<32> next_state8(state8);
-	varint_u<32> next_state9(state9);
-	varint_u<32> next_state10(state10);
-	varint_u<1> next_state11(state11);
-	varint_u<8> next_state12(state12);
-	varint_u<2> next_state3(state3);
-	
-	varint_u<8> assignableVar1;
-	
-	next_state1 = inputdata_AGen_Addr_En;
-	next_state2 = inputdata_AGen_Offset_0;
-	next_state4 = inputdata_AGen_BlockSize_X;
-	next_state5 = inputdata_AGen_Wrap_X;
-	next_state6 = inputdata_AGen_Start_X_Addr;
-	next_state7 = inputdata_AGen_CmdSize;
-	outputdata_cgen_out_0 = varint_u<64>(0x0l);
-	outputvalid_cgen_out_0 = varint_u<1>(0x0l);
-	switch (static_cast<int>(state3)) {
-		case 0:
-			next_state8 = state6;
-			next_state9 = state6;
-			next_state10 = varint_u<32>(state4);
-			if (varint_u<1>(state1 != varint_u<1>(0x0l))) {
-				next_state3 = varint_u<2>(0x1l);
-			}
-			break;
-		case 1:
-			next_state9 = state8;
-			assignableVar1 = state7;
-			if (varint_u<1>(state10 < varint_u<32>(assignableVar1))) {
-				assignableVar1 = varint_u<8>(state10);
-			}
-			if (varint_u<1>((state5 - state8) < varint_u<32>(assignableVar1)) & varint_u<1>((state5 - state8) < state10)) {
-				assignableVar1 = varint_u<8>(state5 - state8);
-				next_state8 = varint_u<32>(0x0l);
-			} else {
-				next_state8 = state8 + varint_u<32>(assignableVar1);
-				if (varint_u<1>(state8 >= varint_u<32>(0x80000000l))) {
-					next_state8 = varint_u<32>(0x7fffffffl) & state8;
-				}
-			}
-			next_state10 = state10 - varint_u<32>(assignableVar1);
-			next_state12 = assignableVar1;
-			next_state11 = varint_u<1>((state10 - varint_u<32>(assignableVar1)) == varint_u<32>(0x0l));
-			next_state3 = varint_u<2>(0x2l);
-			break;
-		case 2:
-			if ((~(varint_u<1>(0x0l) | outputstall_cgen_out_0))) {
-				outputdata_cgen_out_0 = varint_u<1>(state11).cat(varint_u<15>(0x1l)).cat(varint_u<1>(varint_u<1>(0x0l))).cat(varint_u<7>(varint_u<8>(0x1l))).cat(varint_u<8>(state12)).cat(varint_u<1>(0x0l)).cat(varint_u<31>((state9 + varint_u<32>(state2))));
-				outputvalid_cgen_out_0 = (state1).slice<0, 1>();
-				if (state11) {
-					next_state3 = varint_u<2>(0x3l);
-				} else {
-					next_state3 = varint_u<2>(0x1l);
-				}
-			}
-			break;
-	}
-	
-	// update states
-	if (!stall) {
-		state1 = next_state1;
-		state2 = next_state2;
-		state4 = next_state4;
-		state5 = next_state5;
-		state6 = next_state6;
-		state7 = next_state7;
-		state8 = next_state8;
-		state9 = next_state9;
-		state10 = next_state10;
-		state11 = next_state11;
-		state12 = next_state12;
-		state3 = next_state3;
-	}
-	
-}