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@@ -42,7 +42,7 @@ struct starpu_codelet cl =
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}
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\endverbatim
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-\subsection Example StarPU/FPGA Application
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+\subsection FPGAExample StarPU/FPGA Application
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To give you an idea of the interface that we used to exchange data between <c>host</c> (CPU) and <c>FPGA</c> (DFE), here is an example, based on one of the examples of Maxeler (https://trac.version.fz-juelich.de/reconfigurable/wiki/Public).
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<c>StreamFMAKernel.maxj</c> represents the Java kernel code; it implements a very simple kernel (c=a+b), and <c>Test.c</c> starts it from the <c>fpga_add</c> function; it first sets streaming up from the CPU pointers, triggers execution and waits for the result. The API to interact with DFEs is called <c>SLiC</c> which then also involves the <c> MaxelerOS</c> runtime.
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@@ -212,7 +212,7 @@ In the <c>main</c> function, there are four important steps:
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- Free actions.
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- Unload and deallocate the DFE.
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-\subsection Configuration FPGA Configuration
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+\subsection FPGAConfiguration FPGA Configuration
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To configure StarPU with FPGA accelerators, we can enable <c>FPGA</c> through the \c configure option <b>"--with-fpga"</b>.
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@@ -223,7 +223,7 @@ $ make install
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\endverbatim
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-\subsection Launchingprograms Launching Programs: Simulation
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+\subsection FPGALaunchingprograms Launching Programs: Simulation
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Maxeler provides a simple tutorial to use MaxCompiler (https://trac.version.fz-juelich.de/reconfigurable/wiki/Public). Running the Java program to generate maxfile and slic headers (hardware) on Maxeler's DFE device, takes a VERY long time, approx. 2 hours even for this very small example. That's why we use the simulation.
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