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@@ -1,6 +1,6 @@
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/* StarPU --- Runtime system for heterogeneous multicore architectures.
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*
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- * Copyright (C) 2009-2013 Université de Bordeaux 1
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+ * Copyright (C) 2009-2014 Université de Bordeaux 1
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* Copyright (C) 2010, 2011, 2012, 2013 Centre National de la Recherche Scientifique
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* Copyright (C) 2013 Corentin Salingue
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*
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@@ -1398,6 +1398,8 @@ void starpu_bus_print_bandwidth(FILE *f)
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fprintf(f, "CUDA %d\t", dst);
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for (dst = 0; dst < nopencl; dst++)
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fprintf(f, "OpenCL%d\t", dst);
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+ for (dst = 0; dst < nmic; dst++)
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+ fprintf(f, "MIC%d\t", dst);
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fprintf(f, "\n");
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for (src = 0; src <= maxnode; src++)
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@@ -1406,8 +1408,10 @@ void starpu_bus_print_bandwidth(FILE *f)
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fprintf(f, "RAM\t");
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else if (src <= ncuda)
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fprintf(f, "CUDA %d\t", src-1);
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- else
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+ else if (src <= ncuda + nopencl)
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fprintf(f, "OpenCL%d\t", src-ncuda-1);
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+ else
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+ fprintf(f, "MIC%d\t", src-ncuda-nopencl-1);
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for (dst = 0; dst <= maxnode; dst++)
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fprintf(f, "%.0f\t", bandwidth_matrix[src][dst]);
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@@ -1421,8 +1425,10 @@ void starpu_bus_print_bandwidth(FILE *f)
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fprintf(f, "RAM\t");
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else if (src <= ncuda)
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fprintf(f, "CUDA %d\t", src-1);
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- else
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+ else if (src <= ncuda + nopencl)
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fprintf(f, "OpenCL%d\t", src-ncuda-1);
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+ else
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+ fprintf(f, "MIC%d\t", src-ncuda-nopencl-1);
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for (dst = 0; dst <= maxnode; dst++)
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fprintf(f, "%.0f\t", latency_matrix[src][dst]);
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@@ -1432,7 +1438,7 @@ void starpu_bus_print_bandwidth(FILE *f)
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#if defined(STARPU_USE_CUDA) || defined(STARPU_USE_OPENCL)
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if (ncuda != 0 || nopencl != 0)
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fprintf(f, "\nGPU\tCPU in preference order (logical index), host-to-device, device-to-host\n");
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- for (src = 1; src <= maxnode; src++)
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+ for (src = 1; src <= ncuda + nopencl; src++)
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{
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struct dev_timing *timing;
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struct _starpu_machine_config *config = _starpu_get_machine_config();
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