Browse Source

add compatibility with simgrid 3.13

Samuel Thibault 9 years ago
parent
commit
966c035f9e

+ 1 - 1
doc/doxygen/chapters/01building.doxy

@@ -346,7 +346,7 @@ multiplication using BLAS and cuBLAS. They output the obtained GFlops.
 It can also be convenient to try simulated benchmarks, if you want to give a try
 It can also be convenient to try simulated benchmarks, if you want to give a try
 at CPU-GPU scheduling without actually having a GPU at hand. This can be done by
 at CPU-GPU scheduling without actually having a GPU at hand. This can be done by
 using the simgrid version of StarPU: first install the simgrid simulator from
 using the simgrid version of StarPU: first install the simgrid simulator from
-http://simgrid.gforge.inria.fr/ (we tested with simgrid 3.11 and 3.12, other versions
+http://simgrid.gforge.inria.fr/ (we tested with simgrid 3.11, 3.12 and 3.13, other versions
 may have compatibility issues), then configure StarPU with \ref enable-simgrid
 may have compatibility issues), then configure StarPU with \ref enable-simgrid
 "--enable-simgrid" and rebuild and install it, and then you can simulate the performance for a
 "--enable-simgrid" and rebuild and install it, and then you can simulate the performance for a
 few virtualized systems shipped along StarPU: attila, mirage, idgraf, and sirocco.
 few virtualized systems shipped along StarPU: attila, mirage, idgraf, and sirocco.

+ 1 - 1
doc/doxygen/chapters/21simgrid.doxy

@@ -9,7 +9,7 @@
 /*! \page SimGridSupport SimGrid Support
 /*! \page SimGridSupport SimGrid Support
 
 
 StarPU can use Simgrid in order to simulate execution on an arbitrary
 StarPU can use Simgrid in order to simulate execution on an arbitrary
-platform. This was tested with simgrid 3.11 and 3.12, other versions may have
+platform. This was tested with simgrid 3.11, 3.12 and 3.13, other versions may have
 compatibility issues.
 compatibility issues.
 
 
 \section Preparing Preparing your application for simulation.
 \section Preparing Preparing your application for simulation.

+ 2 - 2
src/core/perfmodel/perfmodel.h

@@ -1,6 +1,6 @@
 /* StarPU --- Runtime system for heterogeneous multicore architectures.
 /* StarPU --- Runtime system for heterogeneous multicore architectures.
  *
  *
- * Copyright (C) 2009-2015  Université de Bordeaux
+ * Copyright (C) 2009-2016  Université de Bordeaux
  * Copyright (C) 2010, 2011, 2012, 2013, 2014, 2015  CNRS
  * Copyright (C) 2010, 2011, 2012, 2013, 2014, 2015  CNRS
  * Copyright (C) 2011  Télécom-SudParis
  * Copyright (C) 2011  Télécom-SudParis
  *
  *
@@ -103,7 +103,7 @@ void _starpu_save_bandwidth_and_latency_disk(double bandwidth_write, double band
 
 
 void _starpu_write_double(FILE *f, char *format, double val);
 void _starpu_write_double(FILE *f, char *format, double val);
 int _starpu_read_double(FILE *f, char *format, double *val);
 int _starpu_read_double(FILE *f, char *format, double *val);
-void _starpu_simgrid_get_platform_path(char *path, size_t maxlen);
+void _starpu_simgrid_get_platform_path(int version, char *path, size_t maxlen);
 
 
 struct starpu_perfmodel_arch * _starpu_arch_comb_get(int comb);
 struct starpu_perfmodel_arch * _starpu_arch_comb_get(int comb);
 
 

+ 74 - 41
src/core/perfmodel/perfmodel_bus.c

@@ -1671,9 +1671,12 @@ static void generate_bus_config_file(void)
 }
 }
 #endif /* !SIMGRID */
 #endif /* !SIMGRID */
 
 
-void _starpu_simgrid_get_platform_path(char *path, size_t maxlen)
+void _starpu_simgrid_get_platform_path(int version, char *path, size_t maxlen)
 {
 {
-	get_bus_path("platform.xml", path, maxlen);
+	if (version == 3)
+		get_bus_path("platform.xml", path, maxlen);
+	else
+		get_bus_path("platform.v4.xml", path, maxlen);
 }
 }
 
 
 #ifndef STARPU_SIMGRID
 #ifndef STARPU_SIMGRID
@@ -1890,7 +1893,7 @@ static void emit_pci_dev(FILE *f, struct hwloc_pcidev_attr_s *pcidev)
 }
 }
 
 
 /* Emit the links of the object */
 /* Emit the links of the object */
-static void emit_topology_bandwidths(FILE *f, hwloc_obj_t obj)
+static void emit_topology_bandwidths(FILE *f, hwloc_obj_t obj, const char *Bps, const char *s)
 {
 {
 	unsigned i;
 	unsigned i;
 	if (obj->userdata)
 	if (obj->userdata)
@@ -1902,10 +1905,10 @@ static void emit_topology_bandwidths(FILE *f, hwloc_obj_t obj)
 			/* Uplink */
 			/* Uplink */
 			fprintf(f, "   <link id=\"");
 			fprintf(f, "   <link id=\"");
 			emit_pci_hub(f, obj);
 			emit_pci_hub(f, obj);
-			fprintf(f, " up\" bandwidth=\"%f\" latency=\"0.000000\"/>\n", data->bw_up);
+			fprintf(f, " up\" bandwidth=\"%f%s\" latency=\"0.000000%s\"/>\n", data->bw_up, Bps, s);
 			fprintf(f, "   <link id=\"");
 			fprintf(f, "   <link id=\"");
 			emit_pci_hub(f, obj);
 			emit_pci_hub(f, obj);
-			fprintf(f, " down\" bandwidth=\"%f\" latency=\"0.000000\"/>\n", data->bw_down);
+			fprintf(f, " down\" bandwidth=\"%f%s\" latency=\"0.000000%s\"/>\n", data->bw_down, Bps, s);
 
 
 			/* PCI Switches are assumed to have infinite internal bandwidth */
 			/* PCI Switches are assumed to have infinite internal bandwidth */
 			if (!obj->name || !strstr(obj->name, "Switch"))
 			if (!obj->name || !strstr(obj->name, "Switch"))
@@ -1914,22 +1917,22 @@ static void emit_topology_bandwidths(FILE *f, hwloc_obj_t obj)
 				 * order to support full duplex but not more */
 				 * order to support full duplex but not more */
 				fprintf(f, "   <link id=\"");
 				fprintf(f, "   <link id=\"");
 				emit_pci_hub(f, obj);
 				emit_pci_hub(f, obj);
-				fprintf(f, " through\" bandwidth=\"%f\" latency=\"0.000000\"/>\n", data->bw * 2);
+				fprintf(f, " through\" bandwidth=\"%f%s\" latency=\"0.000000%s\"/>\n", data->bw * 2, Bps, s);
 			}
 			}
 		}
 		}
 		else if (obj->type == HWLOC_OBJ_PCI_DEVICE)
 		else if (obj->type == HWLOC_OBJ_PCI_DEVICE)
 		{
 		{
 			fprintf(f, "   <link id=\"");
 			fprintf(f, "   <link id=\"");
 			emit_pci_dev(f, &obj->attr->pcidev);
 			emit_pci_dev(f, &obj->attr->pcidev);
-			fprintf(f, " up\" bandwidth=\"%f\" latency=\"0.000000\"/>\n", data->bw_up);
+			fprintf(f, " up\" bandwidth=\"%f%s\" latency=\"0.000000%s\"/>\n", data->bw_up, Bps, s);
 			fprintf(f, "   <link id=\"");
 			fprintf(f, "   <link id=\"");
 			emit_pci_dev(f, &obj->attr->pcidev);
 			emit_pci_dev(f, &obj->attr->pcidev);
-			fprintf(f, " down\" bandwidth=\"%f\" latency=\"0.000000\"/>\n", data->bw_down);
+			fprintf(f, " down\" bandwidth=\"%f%s\" latency=\"0.000000%s\"/>\n", data->bw_down, Bps, s);
 		}
 		}
 	}
 	}
 
 
 	for (i = 0; i < obj->arity; i++)
 	for (i = 0; i < obj->arity; i++)
-		emit_topology_bandwidths(f, obj->children[i]);
+		emit_topology_bandwidths(f, obj->children[i], Bps, s);
 }
 }
 
 
 /* emit_pci_link_* functions perform the third step: emitting the routes */
 /* emit_pci_link_* functions perform the third step: emitting the routes */
@@ -2098,15 +2101,34 @@ static void clean_topology(hwloc_obj_t obj)
 }
 }
 #endif
 #endif
 
 
-static void write_bus_platform_file_content(void)
+static void write_bus_platform_file_content(int version)
 {
 {
 	FILE *f;
 	FILE *f;
 	char path[256];
 	char path[256];
 	unsigned i;
 	unsigned i;
+	const char *speed, *flops, *Bps, *s;
+	char dash;
+
+	if (version == 3)
+	{
+		speed = "power";
+		flops = "";
+		Bps = "";
+		s = "";
+		dash = '_';
+	}
+	else
+	{
+		speed = "speed";
+		flops = "f";
+		Bps = "Bps";
+		s = "s";
+		dash = '-';
+	}
 
 
 	STARPU_ASSERT(was_benchmarked);
 	STARPU_ASSERT(was_benchmarked);
 
 
-	_starpu_simgrid_get_platform_path(path, sizeof(path));
+	_starpu_simgrid_get_platform_path(version, path, sizeof(path));
 
 
 	_STARPU_DEBUG("writing platform to %s\n", path);
 	_STARPU_DEBUG("writing platform to %s\n", path);
 
 
@@ -2123,24 +2145,27 @@ static void write_bus_platform_file_content(void)
 
 
 	fprintf(f,
 	fprintf(f,
 "<?xml version='1.0'?>\n"
 "<?xml version='1.0'?>\n"
-" <!DOCTYPE platform SYSTEM 'http://simgrid.gforge.inria.fr/simgrid.dtd'>\n"
+"<!DOCTYPE platform SYSTEM '%s'>\n"
-" <platform version=\"3\">\n"
+" <platform version=\"%u\">\n"
 " <config id=\"General\">\n"
 " <config id=\"General\">\n"
-"   <prop id=\"network/TCP_gamma\" value=\"-1\"></prop>\n"
+"   <prop id=\"network/TCP%cgamma\" value=\"-1\"></prop>\n"
-"   <prop id=\"network/latency_factor\" value=\"1\"></prop>\n"
+"   <prop id=\"network/latency%cfactor\" value=\"1\"></prop>\n"
-"   <prop id=\"network/bandwidth_factor\" value=\"1\"></prop>\n"
+"   <prop id=\"network/bandwidth%cfactor\" value=\"1\"></prop>\n"
 " </config>\n"
 " </config>\n"
 " <AS  id=\"AS0\"  routing=\"Full\">\n"
 " <AS  id=\"AS0\"  routing=\"Full\">\n"
-"   <host id=\"MAIN\" power=\"1\"/>\n"
+"   <host id=\"MAIN\" %s=\"1%s\"/>\n",
-		);
+		version == 3
+			? "http://simgrid.gforge.inria.fr/simgrid.dtd"
+			: "http://simgrid.gforge.inria.fr/simgrid/simgrid.dtd",
+		version, dash, dash, dash, speed, flops);
 
 
 	for (i = 0; i < ncpus; i++)
 	for (i = 0; i < ncpus; i++)
 		/* TODO: host memory for out-of-core simulation */
 		/* TODO: host memory for out-of-core simulation */
-		fprintf(f, "   <host id=\"CPU%d\" power=\"2000000000\"/>\n", i);
+		fprintf(f, "   <host id=\"CPU%d\" %s=\"2000000000%s\"/>\n", i, speed, flops);
 
 
 	for (i = 0; i < ncuda; i++)
 	for (i = 0; i < ncuda; i++)
 	{
 	{
-		fprintf(f, "   <host id=\"CUDA%d\" power=\"2000000000\">\n", i);
+		fprintf(f, "   <host id=\"CUDA%d\" %s=\"2000000000%s\">\n", i, speed, flops);
 		fprintf(f, "     <prop id=\"memsize\" value=\"%llu\"/>\n", (unsigned long long) cuda_size[i]);
 		fprintf(f, "     <prop id=\"memsize\" value=\"%llu\"/>\n", (unsigned long long) cuda_size[i]);
 #ifdef HAVE_CUDA_MEMCPY_PEER
 #ifdef HAVE_CUDA_MEMCPY_PEER
 		fprintf(f, "     <prop id=\"memcpy_peer\" value=\"1\"/>\n");
 		fprintf(f, "     <prop id=\"memcpy_peer\" value=\"1\"/>\n");
@@ -2150,12 +2175,12 @@ static void write_bus_platform_file_content(void)
 
 
 	for (i = 0; i < nopencl; i++)
 	for (i = 0; i < nopencl; i++)
 	{
 	{
-		fprintf(f, "   <host id=\"OpenCL%d\" power=\"2000000000\">\n", i);
+		fprintf(f, "   <host id=\"OpenCL%d\" %s=\"2000000000%s\">\n", i, speed, flops);
 		fprintf(f, "     <prop id=\"memsize\" value=\"%llu\"/>\n", (unsigned long long) opencl_size[i]);
 		fprintf(f, "     <prop id=\"memsize\" value=\"%llu\"/>\n", (unsigned long long) opencl_size[i]);
 		fprintf(f, "   </host>\n");
 		fprintf(f, "   </host>\n");
 	}
 	}
 
 
-	fprintf(f, "\n   <host id=\"RAM\" power=\"1\"/>\n");
+	fprintf(f, "\n   <host id=\"RAM\" %s=\"1%s\"/>\n", speed, flops);
 
 
 	/*
 	/*
 	 * Compute maximum bandwidth, taken as host bandwidth
 	 * Compute maximum bandwidth, taken as host bandwidth
@@ -2183,7 +2208,7 @@ static void write_bus_platform_file_content(void)
 			max_bandwidth = up_bw;
 			max_bandwidth = up_bw;
 	}
 	}
 #endif
 #endif
-	fprintf(f, "\n   <link id=\"Host\" bandwidth=\"%f\" latency=\"0.000000\"/>\n\n", max_bandwidth*1000000);
+	fprintf(f, "\n   <link id=\"Host\" bandwidth=\"%f%s\" latency=\"0.000000%s\"/>\n\n", max_bandwidth*1000000, Bps, s);
 
 
 	/*
 	/*
 	 * OpenCL links
 	 * OpenCL links
@@ -2194,14 +2219,14 @@ static void write_bus_platform_file_content(void)
 	{
 	{
 		char i_name[16];
 		char i_name[16];
 		snprintf(i_name, sizeof(i_name), "OpenCL%d", i);
 		snprintf(i_name, sizeof(i_name), "OpenCL%d", i);
-		fprintf(f, "   <link id=\"RAM-%s\" bandwidth=\"%f\" latency=\"%f\"/>\n",
+		fprintf(f, "   <link id=\"RAM-%s\" bandwidth=\"%f%s\" latency=\"%f%s\"/>\n",
 			i_name,
 			i_name,
-			1000000 / opencldev_timing_htod[1+i],
+			1000000 / opencldev_timing_htod[1+i], Bps,
-			opencldev_latency_htod[1+i]/1000000.);
+			opencldev_latency_htod[1+i]/1000000., s);
-		fprintf(f, "   <link id=\"%s-RAM\" bandwidth=\"%f\" latency=\"%f\"/>\n",
+		fprintf(f, "   <link id=\"%s-RAM\" bandwidth=\"%f%s\" latency=\"%f%s\"/>\n",
 			i_name,
 			i_name,
-			1000000 / opencldev_timing_dtoh[1+i],
+			1000000 / opencldev_timing_dtoh[1+i], Bps,
-			opencldev_latency_dtoh[1+i]/1000000.);
+			opencldev_latency_dtoh[1+i]/1000000., s);
 	}
 	}
 	fprintf(f, "\n");
 	fprintf(f, "\n");
 #endif
 #endif
@@ -2216,14 +2241,14 @@ static void write_bus_platform_file_content(void)
 	{
 	{
 		char i_name[16];
 		char i_name[16];
 		snprintf(i_name, sizeof(i_name), "CUDA%d", i);
 		snprintf(i_name, sizeof(i_name), "CUDA%d", i);
-		fprintf(f, "   <link id=\"RAM-%s\" bandwidth=\"%f\" latency=\"%f\"/>\n",
+		fprintf(f, "   <link id=\"RAM-%s\" bandwidth=\"%f%s\" latency=\"%f%s\"/>\n",
 			i_name,
 			i_name,
-			1000000. / cudadev_timing_htod[1+i],
+			1000000. / cudadev_timing_htod[1+i], Bps,
-			cudadev_latency_htod[1+i]/1000000.);
+			cudadev_latency_htod[1+i]/1000000., s);
-		fprintf(f, "   <link id=\"%s-RAM\" bandwidth=\"%f\" latency=\"%f\"/>\n",
+		fprintf(f, "   <link id=\"%s-RAM\" bandwidth=\"%f%s\" latency=\"%f%s\"/>\n",
 			i_name,
 			i_name,
-			1000000. / cudadev_timing_dtoh[1+i],
+			1000000. / cudadev_timing_dtoh[1+i], Bps,
-			cudadev_latency_dtoh[1+i]/1000000.);
+			cudadev_latency_dtoh[1+i]/1000000., s);
 	}
 	}
 	fprintf(f, "\n");
 	fprintf(f, "\n");
 #ifdef HAVE_CUDA_MEMCPY_PEER
 #ifdef HAVE_CUDA_MEMCPY_PEER
@@ -2239,10 +2264,10 @@ static void write_bus_platform_file_content(void)
 			if (j == i)
 			if (j == i)
 				continue;
 				continue;
 			snprintf(j_name, sizeof(j_name), "CUDA%d", j);
 			snprintf(j_name, sizeof(j_name), "CUDA%d", j);
-			fprintf(f, "   <link id=\"%s-%s\" bandwidth=\"%f\" latency=\"%f\"/>\n",
+			fprintf(f, "   <link id=\"%s-%s\" bandwidth=\"%f%s\" latency=\"%f%s\"/>\n",
 				i_name, j_name,
 				i_name, j_name,
-				1000000. / cudadev_timing_dtod[1+i][1+j],
+				1000000. / cudadev_timing_dtod[1+i][1+j], Bps,
-				cudadev_latency_dtod[1+i][1+j]/1000000.);
+				cudadev_latency_dtod[1+i][1+j]/1000000., s);
 		}
 		}
 	}
 	}
 #endif
 #endif
@@ -2275,7 +2300,7 @@ static void write_bus_platform_file_content(void)
 
 
 		/* Ok, found path in all cases, can emit advanced platform routes */
 		/* Ok, found path in all cases, can emit advanced platform routes */
 		fprintf(f, "\n");
 		fprintf(f, "\n");
-		emit_topology_bandwidths(f, hwloc_get_root_obj(topology));
+		emit_topology_bandwidths(f, hwloc_get_root_obj(topology), Bps, s);
 		fprintf(f, "\n");
 		fprintf(f, "\n");
 		for (i = 0; i < ncuda; i++)
 		for (i = 0; i < ncuda; i++)
 		{
 		{
@@ -2367,7 +2392,8 @@ static void generate_bus_platform_file(void)
 	if (!was_benchmarked)
 	if (!was_benchmarked)
 		benchmark_all_gpu_devices();
 		benchmark_all_gpu_devices();
 
 
-	write_bus_platform_file_content();
+	write_bus_platform_file_content(3);
+	write_bus_platform_file_content(4);
 }
 }
 
 
 static void check_bus_platform_file(void)
 static void check_bus_platform_file(void)
@@ -2375,9 +2401,16 @@ static void check_bus_platform_file(void)
 	int res;
 	int res;
 
 
 	char path[256];
 	char path[256];
-	_starpu_simgrid_get_platform_path(path, sizeof(path));
+	_starpu_simgrid_get_platform_path(4, path, sizeof(path));
 
 
 	res = access(path, F_OK);
 	res = access(path, F_OK);
+
+	if (res)
+	{
+		_starpu_simgrid_get_platform_path(3, path, sizeof(path));
+		res = access(path, F_OK);
+	}
+
 	if (res)
 	if (res)
 	{
 	{
 		/* File does not exist yet */
 		/* File does not exist yet */

+ 5 - 1
src/core/simgrid.c

@@ -232,7 +232,11 @@ int main(int argc, char **argv)
 #endif
 #endif
 
 
 	/* Load XML platform */
 	/* Load XML platform */
-	_starpu_simgrid_get_platform_path(path, sizeof(path));
+#if SIMGRID_VERSION_MAJOR < 3 || (SIMGRID_VERSION_MAJOR == 3 && SIMGRID_VERSION_MINOR < 13)
+	_starpu_simgrid_get_platform_path(3, path, sizeof(path));
+#else
+	_starpu_simgrid_get_platform_path(4, path, sizeof(path));
+#endif
 	MSG_create_environment(path);
 	MSG_create_environment(path);
 
 
 	struct main_args *args = malloc(sizeof(*args));
 	struct main_args *args = malloc(sizeof(*args));

+ 2 - 2
src/core/simgrid.h

@@ -1,6 +1,6 @@
 /* StarPU --- Runtime system for heterogeneous multicore architectures.
 /* StarPU --- Runtime system for heterogeneous multicore architectures.
  *
  *
- * Copyright (C) 2012-2015  Université de Bordeaux
+ * Copyright (C) 2012-2016  Université de Bordeaux
  *
  *
  * StarPU is free software; you can redistribute it and/or modify
  * StarPU is free software; you can redistribute it and/or modify
  * it under the terms of the GNU Lesser General Public License as published by
  * it under the terms of the GNU Lesser General Public License as published by
@@ -47,7 +47,7 @@ unsigned long long _starpu_simgrid_get_memsize(const char *prefix, unsigned devi
 msg_host_t _starpu_simgrid_get_host_by_name(const char *name);
 msg_host_t _starpu_simgrid_get_host_by_name(const char *name);
 struct _starpu_worker;
 struct _starpu_worker;
 msg_host_t _starpu_simgrid_get_host_by_worker(struct _starpu_worker *worker);
 msg_host_t _starpu_simgrid_get_host_by_worker(struct _starpu_worker *worker);
-void _starpu_simgrid_get_platform_path(char *path, size_t maxlen);
+void _starpu_simgrid_get_platform_path(int version, char *path, size_t maxlen);
 msg_as_t _starpu_simgrid_get_as_by_name(const char *name);
 msg_as_t _starpu_simgrid_get_as_by_name(const char *name);
 #pragma weak starpu_mpi_world_rank
 #pragma weak starpu_mpi_world_rank
 extern int starpu_mpi_world_rank(void);
 extern int starpu_mpi_world_rank(void);

+ 236 - 0
tools/perfmodels/sampling/bus/attila.platform.v4.xml

@@ -0,0 +1,236 @@
+<?xml version='1.0'?>
+<!DOCTYPE platform SYSTEM "http://simgrid.gforge.inria.fr/simgrid/simgrid.dtd">
+<platform version="4">
+ 
+ 
+ <config id="General">
+   <prop id="network/TCP-gamma" value="-1"></prop>
+   <prop id="network/latency-factor" value="1"></prop>
+   <prop id="network/bandwidth-factor" value="1"></prop>
+ </config>
+ <AS  id="AS0"  routing="Full">
+   <host id="MAIN" speed="1f"/>
+   <host id="CPU0" speed="2000000000f"/>
+   <host id="CPU1" speed="2000000000f"/>
+   <host id="CPU2" speed="2000000000f"/>
+   <host id="CPU3" speed="2000000000f"/>
+   <host id="CPU4" speed="2000000000f"/>
+   <host id="CPU5" speed="2000000000f"/>
+   <host id="CPU6" speed="2000000000f"/>
+   <host id="CPU7" speed="2000000000f"/>
+   <host id="CPU8" speed="2000000000f"/>
+   <host id="CPU9" speed="2000000000f"/>
+   <host id="CPU10" speed="2000000000f"/>
+   <host id="CPU11" speed="2000000000f"/>
+   <host id="CUDA0" speed="2000000000f">
+     <prop id="memsize" value="3220897792"/>
+     <prop id="memcpy_peer" value="1"/>
+   </host>
+   <host id="CUDA1" speed="2000000000f">
+     <prop id="memsize" value="3220897792"/>
+     <prop id="memcpy_peer" value="1"/>
+   </host>
+   <host id="CUDA2" speed="2000000000f">
+     <prop id="memsize" value="3220897792"/>
+     <prop id="memcpy_peer" value="1"/>
+   </host>
+   <host id="OpenCL0" speed="2000000000f">
+     <prop id="memsize" value="3220897792"/>
+   </host>
+   <host id="OpenCL1" speed="2000000000f">
+     <prop id="memsize" value="3220897792"/>
+   </host>
+   <host id="OpenCL2" speed="2000000000f">
+     <prop id="memsize" value="3220897792"/>
+   </host>
+
+   <host id="RAM" speed="1f"/>
+
+   <link id="Host" bandwidth="6526732233.112210Bps" latency="0.000000s"/>
+
+   <link id="RAM-OpenCL0" bandwidth="4162285174.177163Bps" latency="0.000010s"/>
+   <link id="OpenCL0-RAM" bandwidth="4459645563.963992Bps" latency="0.000014s"/>
+   <link id="RAM-OpenCL1" bandwidth="3828575609.690533Bps" latency="0.000010s"/>
+   <link id="OpenCL1-RAM" bandwidth="3420625686.373279Bps" latency="0.000014s"/>
+   <link id="RAM-OpenCL2" bandwidth="3867164138.727851Bps" latency="0.000010s"/>
+   <link id="OpenCL2-RAM" bandwidth="3873346625.166936Bps" latency="0.000015s"/>
+
+   <link id="RAM-CUDA0" bandwidth="6008661719.001335Bps" latency="0.000009s"/>
+   <link id="CUDA0-RAM" bandwidth="6526024509.281727Bps" latency="0.000010s"/>
+   <link id="RAM-CUDA1" bandwidth="6001134065.085753Bps" latency="0.000009s"/>
+   <link id="CUDA1-RAM" bandwidth="6526732233.112210Bps" latency="0.000010s"/>
+   <link id="RAM-CUDA2" bandwidth="5231971524.585075Bps" latency="0.000010s"/>
+   <link id="CUDA2-RAM" bandwidth="4519044753.742499Bps" latency="0.000011s"/>
+
+   <link id="CUDA0-CUDA1" bandwidth="5296862725.591065Bps" latency="0.000015s"/>
+   <link id="CUDA0-CUDA2" bandwidth="3792200896.189628Bps" latency="0.000025s"/>
+   <link id="CUDA1-CUDA0" bandwidth="5297288565.963223Bps" latency="0.000014s"/>
+   <link id="CUDA1-CUDA2" bandwidth="3800896492.025119Bps" latency="0.000024s"/>
+   <link id="CUDA2-CUDA0" bandwidth="3068730935.113825Bps" latency="0.000023s"/>
+   <link id="CUDA2-CUDA1" bandwidth="3067648325.986417Bps" latency="0.000023s"/>
+
+   <link id="PCI:0000:[00-07] up" bandwidth="6526732233.112210Bps" latency="0.000000s"/>
+   <link id="PCI:0000:[00-07] down" bandwidth="6008661719.001335Bps" latency="0.000000s"/>
+   <link id="PCI:0000:[00-07] through" bandwidth="13053464466.224421Bps" latency="0.000000s"/>
+   <link id="PCI:0000:[02-02] up" bandwidth="6526024509.281727Bps" latency="0.000000s"/>
+   <link id="PCI:0000:[02-02] down" bandwidth="6008661719.001335Bps" latency="0.000000s"/>
+   <link id="PCI:0000:[02-02] through" bandwidth="13052049018.563454Bps" latency="0.000000s"/>
+   <link id="PCI:0000:02:00.0 up" bandwidth="6526024509.281727Bps" latency="0.000000s"/>
+   <link id="PCI:0000:02:00.0 down" bandwidth="6008661719.001335Bps" latency="0.000000s"/>
+   <link id="PCI:0000:[03-03] up" bandwidth="6526732233.112210Bps" latency="0.000000s"/>
+   <link id="PCI:0000:[03-03] down" bandwidth="6001134065.085753Bps" latency="0.000000s"/>
+   <link id="PCI:0000:[03-03] through" bandwidth="13053464466.224421Bps" latency="0.000000s"/>
+   <link id="PCI:0000:03:00.0 up" bandwidth="6526732233.112210Bps" latency="0.000000s"/>
+   <link id="PCI:0000:03:00.0 down" bandwidth="6001134065.085753Bps" latency="0.000000s"/>
+   <link id="PCI:0000:[80-84] up" bandwidth="4519044753.742499Bps" latency="0.000000s"/>
+   <link id="PCI:0000:[80-84] down" bandwidth="5231971524.585075Bps" latency="0.000000s"/>
+   <link id="PCI:0000:[80-84] through" bandwidth="10463943049.170151Bps" latency="0.000000s"/>
+   <link id="PCI:0000:[84-84] up" bandwidth="4519044753.742499Bps" latency="0.000000s"/>
+   <link id="PCI:0000:[84-84] down" bandwidth="5231971524.585075Bps" latency="0.000000s"/>
+   <link id="PCI:0000:[84-84] through" bandwidth="10463943049.170151Bps" latency="0.000000s"/>
+   <link id="PCI:0000:84:00.0 up" bandwidth="4519044753.742499Bps" latency="0.000000s"/>
+   <link id="PCI:0000:84:00.0 down" bandwidth="5231971524.585075Bps" latency="0.000000s"/>
+
+   <route src="CUDA0" dst="CUDA1" symmetrical="NO">
+    <link_ctn id="CUDA0-CUDA1"/>
+    <link_ctn id="PCI:0000:03:00.0 down"/>
+    <link_ctn id="PCI:0000:[03-03] through"/>
+    <link_ctn id="PCI:0000:[03-03] down"/>
+    <link_ctn id="PCI:0000:[00-07] through"/>
+    <link_ctn id="PCI:0000:[02-02] up"/>
+    <link_ctn id="PCI:0000:[02-02] through"/>
+    <link_ctn id="PCI:0000:02:00.0 up"/>
+   </route>
+   <route src="CUDA0" dst="CUDA2" symmetrical="NO">
+    <link_ctn id="CUDA0-CUDA2"/>
+    <link_ctn id="PCI:0000:84:00.0 down"/>
+    <link_ctn id="PCI:0000:[84-84] through"/>
+    <link_ctn id="PCI:0000:[84-84] down"/>
+    <link_ctn id="PCI:0000:[80-84] through"/>
+    <link_ctn id="PCI:0000:[80-84] down"/>
+    <link_ctn id="Host"/>
+    <link_ctn id="Host"/>
+    <link_ctn id="PCI:0000:[00-07] up"/>
+    <link_ctn id="PCI:0000:[00-07] through"/>
+    <link_ctn id="PCI:0000:[02-02] up"/>
+    <link_ctn id="PCI:0000:[02-02] through"/>
+    <link_ctn id="PCI:0000:02:00.0 up"/>
+   </route>
+   <route src="CUDA0" dst="RAM" symmetrical="NO">
+    <link_ctn id="CUDA0-RAM"/>
+    <link_ctn id="PCI:0000:02:00.0 up"/>
+    <link_ctn id="PCI:0000:[02-02] through"/>
+    <link_ctn id="PCI:0000:[02-02] up"/>
+    <link_ctn id="PCI:0000:[00-07] through"/>
+    <link_ctn id="PCI:0000:[00-07] up"/>
+    <link_ctn id="Host"/>
+   </route>
+   <route src="RAM" dst="CUDA0" symmetrical="NO">
+    <link_ctn id="RAM-CUDA0"/>
+    <link_ctn id="PCI:0000:02:00.0 down"/>
+    <link_ctn id="PCI:0000:[02-02] through"/>
+    <link_ctn id="PCI:0000:[02-02] down"/>
+    <link_ctn id="PCI:0000:[00-07] through"/>
+    <link_ctn id="PCI:0000:[00-07] down"/>
+    <link_ctn id="Host"/>
+   </route>
+   <route src="CUDA1" dst="CUDA0" symmetrical="NO">
+    <link_ctn id="CUDA1-CUDA0"/>
+    <link_ctn id="PCI:0000:02:00.0 down"/>
+    <link_ctn id="PCI:0000:[02-02] through"/>
+    <link_ctn id="PCI:0000:[02-02] down"/>
+    <link_ctn id="PCI:0000:[00-07] through"/>
+    <link_ctn id="PCI:0000:[03-03] up"/>
+    <link_ctn id="PCI:0000:[03-03] through"/>
+    <link_ctn id="PCI:0000:03:00.0 up"/>
+   </route>
+   <route src="CUDA1" dst="CUDA2" symmetrical="NO">
+    <link_ctn id="CUDA1-CUDA2"/>
+    <link_ctn id="PCI:0000:84:00.0 down"/>
+    <link_ctn id="PCI:0000:[84-84] through"/>
+    <link_ctn id="PCI:0000:[84-84] down"/>
+    <link_ctn id="PCI:0000:[80-84] through"/>
+    <link_ctn id="PCI:0000:[80-84] down"/>
+    <link_ctn id="Host"/>
+    <link_ctn id="Host"/>
+    <link_ctn id="PCI:0000:[00-07] up"/>
+    <link_ctn id="PCI:0000:[00-07] through"/>
+    <link_ctn id="PCI:0000:[03-03] up"/>
+    <link_ctn id="PCI:0000:[03-03] through"/>
+    <link_ctn id="PCI:0000:03:00.0 up"/>
+   </route>
+   <route src="CUDA1" dst="RAM" symmetrical="NO">
+    <link_ctn id="CUDA1-RAM"/>
+    <link_ctn id="PCI:0000:03:00.0 up"/>
+    <link_ctn id="PCI:0000:[03-03] through"/>
+    <link_ctn id="PCI:0000:[03-03] up"/>
+    <link_ctn id="PCI:0000:[00-07] through"/>
+    <link_ctn id="PCI:0000:[00-07] up"/>
+    <link_ctn id="Host"/>
+   </route>
+   <route src="RAM" dst="CUDA1" symmetrical="NO">
+    <link_ctn id="RAM-CUDA1"/>
+    <link_ctn id="PCI:0000:03:00.0 down"/>
+    <link_ctn id="PCI:0000:[03-03] through"/>
+    <link_ctn id="PCI:0000:[03-03] down"/>
+    <link_ctn id="PCI:0000:[00-07] through"/>
+    <link_ctn id="PCI:0000:[00-07] down"/>
+    <link_ctn id="Host"/>
+   </route>
+   <route src="CUDA2" dst="CUDA0" symmetrical="NO">
+    <link_ctn id="CUDA2-CUDA0"/>
+    <link_ctn id="PCI:0000:02:00.0 down"/>
+    <link_ctn id="PCI:0000:[02-02] through"/>
+    <link_ctn id="PCI:0000:[02-02] down"/>
+    <link_ctn id="PCI:0000:[00-07] through"/>
+    <link_ctn id="PCI:0000:[00-07] down"/>
+    <link_ctn id="Host"/>
+    <link_ctn id="Host"/>
+    <link_ctn id="PCI:0000:[80-84] up"/>
+    <link_ctn id="PCI:0000:[80-84] through"/>
+    <link_ctn id="PCI:0000:[84-84] up"/>
+    <link_ctn id="PCI:0000:[84-84] through"/>
+    <link_ctn id="PCI:0000:84:00.0 up"/>
+   </route>
+   <route src="CUDA2" dst="CUDA1" symmetrical="NO">
+    <link_ctn id="CUDA2-CUDA1"/>
+    <link_ctn id="PCI:0000:03:00.0 down"/>
+    <link_ctn id="PCI:0000:[03-03] through"/>
+    <link_ctn id="PCI:0000:[03-03] down"/>
+    <link_ctn id="PCI:0000:[00-07] through"/>
+    <link_ctn id="PCI:0000:[00-07] down"/>
+    <link_ctn id="Host"/>
+    <link_ctn id="Host"/>
+    <link_ctn id="PCI:0000:[80-84] up"/>
+    <link_ctn id="PCI:0000:[80-84] through"/>
+    <link_ctn id="PCI:0000:[84-84] up"/>
+    <link_ctn id="PCI:0000:[84-84] through"/>
+    <link_ctn id="PCI:0000:84:00.0 up"/>
+   </route>
+   <route src="CUDA2" dst="RAM" symmetrical="NO">
+    <link_ctn id="CUDA2-RAM"/>
+    <link_ctn id="PCI:0000:84:00.0 up"/>
+    <link_ctn id="PCI:0000:[84-84] through"/>
+    <link_ctn id="PCI:0000:[84-84] up"/>
+    <link_ctn id="PCI:0000:[80-84] through"/>
+    <link_ctn id="PCI:0000:[80-84] up"/>
+    <link_ctn id="Host"/>
+   </route>
+   <route src="RAM" dst="CUDA2" symmetrical="NO">
+    <link_ctn id="RAM-CUDA2"/>
+    <link_ctn id="PCI:0000:84:00.0 down"/>
+    <link_ctn id="PCI:0000:[84-84] through"/>
+    <link_ctn id="PCI:0000:[84-84] down"/>
+    <link_ctn id="PCI:0000:[80-84] through"/>
+    <link_ctn id="PCI:0000:[80-84] down"/>
+    <link_ctn id="Host"/>
+   </route>
+
+   <route src="RAM" dst="OpenCL0" symmetrical="NO"><link_ctn id="RAM-OpenCL0"/><link_ctn id="Host"/></route>
+   <route src="OpenCL0" dst="RAM" symmetrical="NO"><link_ctn id="OpenCL0-RAM"/><link_ctn id="Host"/></route>
+   <route src="RAM" dst="OpenCL1" symmetrical="NO"><link_ctn id="RAM-OpenCL1"/><link_ctn id="Host"/></route>
+   <route src="OpenCL1" dst="RAM" symmetrical="NO"><link_ctn id="OpenCL1-RAM"/><link_ctn id="Host"/></route>
+   <route src="RAM" dst="OpenCL2" symmetrical="NO"><link_ctn id="RAM-OpenCL2"/><link_ctn id="Host"/></route>
+   <route src="OpenCL2" dst="RAM" symmetrical="NO"><link_ctn id="OpenCL2-RAM"/><link_ctn id="Host"/></route>
+ </AS>
+ </platform>

File diff suppressed because it is too large
+ 1509 - 0
tools/perfmodels/sampling/bus/idgraf.platform.v4.xml


+ 236 - 0
tools/perfmodels/sampling/bus/mirage.platform.v4.xml

@@ -0,0 +1,236 @@
+<?xml version='1.0'?>
+<!DOCTYPE platform SYSTEM "http://simgrid.gforge.inria.fr/simgrid/simgrid.dtd">
+<platform version="4">
+ 
+ 
+ <config id="General">
+   <prop id="network/TCP-gamma" value="-1"></prop>
+   <prop id="network/latency-factor" value="1"></prop>
+   <prop id="network/bandwidth-factor" value="1"></prop>
+ </config>
+ <AS  id="AS0"  routing="Full">
+   <host id="MAIN" speed="1f"/>
+   <host id="CPU0" speed="2000000000f"/>
+   <host id="CPU1" speed="2000000000f"/>
+   <host id="CPU2" speed="2000000000f"/>
+   <host id="CPU3" speed="2000000000f"/>
+   <host id="CPU4" speed="2000000000f"/>
+   <host id="CPU5" speed="2000000000f"/>
+   <host id="CPU6" speed="2000000000f"/>
+   <host id="CPU7" speed="2000000000f"/>
+   <host id="CPU8" speed="2000000000f"/>
+   <host id="CPU9" speed="2000000000f"/>
+   <host id="CPU10" speed="2000000000f"/>
+   <host id="CPU11" speed="2000000000f"/>
+   <host id="CUDA0" speed="2000000000f">
+     <prop id="memsize" value="5636554752"/>
+     <prop id="memcpy_peer" value="1"/>
+   </host>
+   <host id="CUDA1" speed="2000000000f">
+     <prop id="memsize" value="5636554752"/>
+     <prop id="memcpy_peer" value="1"/>
+   </host>
+   <host id="CUDA2" speed="2000000000f">
+     <prop id="memsize" value="5636554752"/>
+     <prop id="memcpy_peer" value="1"/>
+   </host>
+   <host id="OpenCL0" speed="2000000000f">
+     <prop id="memsize" value="5636554752"/>
+   </host>
+   <host id="OpenCL1" speed="2000000000f">
+     <prop id="memsize" value="5636554752"/>
+   </host>
+   <host id="OpenCL2" speed="2000000000f">
+     <prop id="memsize" value="5636554752"/>
+   </host>
+
+   <host id="RAM" speed="1f"/>
+
+   <link id="Host" bandwidth="6517450307.894589Bps" latency="0.000000s"/>
+
+   <link id="RAM-OpenCL0" bandwidth="4594990014.604123Bps" latency="0.000011s"/>
+   <link id="OpenCL0-RAM" bandwidth="4467527948.677606Bps" latency="0.000016s"/>
+   <link id="RAM-OpenCL1" bandwidth="4562733739.169294Bps" latency="0.000011s"/>
+   <link id="OpenCL1-RAM" bandwidth="4463866496.570195Bps" latency="0.000016s"/>
+   <link id="RAM-OpenCL2" bandwidth="4662066166.976132Bps" latency="0.000011s"/>
+   <link id="OpenCL2-RAM" bandwidth="4446906801.828301Bps" latency="0.000015s"/>
+
+   <link id="RAM-CUDA0" bandwidth="6010679672.232608Bps" latency="0.000010s"/>
+   <link id="CUDA0-RAM" bandwidth="6517450307.894588Bps" latency="0.000011s"/>
+   <link id="RAM-CUDA1" bandwidth="6010515983.677648Bps" latency="0.000010s"/>
+   <link id="CUDA1-RAM" bandwidth="6516266098.599698Bps" latency="0.000011s"/>
+   <link id="RAM-CUDA2" bandwidth="6004390320.608641Bps" latency="0.000010s"/>
+   <link id="CUDA2-RAM" bandwidth="6517036962.443331Bps" latency="0.000011s"/>
+
+   <link id="CUDA0-CUDA1" bandwidth="3078938822.428410Bps" latency="0.000024s"/>
+   <link id="CUDA0-CUDA2" bandwidth="3079244316.374852Bps" latency="0.000024s"/>
+   <link id="CUDA1-CUDA0" bandwidth="3812979795.084610Bps" latency="0.000025s"/>
+   <link id="CUDA1-CUDA2" bandwidth="5296219864.637116Bps" latency="0.000016s"/>
+   <link id="CUDA2-CUDA0" bandwidth="3812868043.274849Bps" latency="0.000025s"/>
+   <link id="CUDA2-CUDA1" bandwidth="5296218780.510124Bps" latency="0.000016s"/>
+
+   <link id="PCI:0000:[00-0f] up" bandwidth="6517450307.894588Bps" latency="0.000000s"/>
+   <link id="PCI:0000:[00-0f] down" bandwidth="6010679672.232608Bps" latency="0.000000s"/>
+   <link id="PCI:0000:[00-0f] through" bandwidth="13034900615.789177Bps" latency="0.000000s"/>
+   <link id="PCI:0000:[06-08] up" bandwidth="6517450307.894588Bps" latency="0.000000s"/>
+   <link id="PCI:0000:[06-08] down" bandwidth="6010679672.232608Bps" latency="0.000000s"/>
+   <link id="PCI:0000:[06-08] through" bandwidth="13034900615.789177Bps" latency="0.000000s"/>
+   <link id="PCI:0000:06:00.0 up" bandwidth="6517450307.894588Bps" latency="0.000000s"/>
+   <link id="PCI:0000:06:00.0 down" bandwidth="6010679672.232608Bps" latency="0.000000s"/>
+   <link id="PCI:0000:[10-1f] up" bandwidth="6517036962.443331Bps" latency="0.000000s"/>
+   <link id="PCI:0000:[10-1f] down" bandwidth="6010515983.677648Bps" latency="0.000000s"/>
+   <link id="PCI:0000:[10-1f] through" bandwidth="13034073924.886662Bps" latency="0.000000s"/>
+   <link id="PCI:0000:[14-16] up" bandwidth="6516266098.599698Bps" latency="0.000000s"/>
+   <link id="PCI:0000:[14-16] down" bandwidth="6010515983.677648Bps" latency="0.000000s"/>
+   <link id="PCI:0000:[14-16] through" bandwidth="13032532197.199396Bps" latency="0.000000s"/>
+   <link id="PCI:0000:14:00.0 up" bandwidth="6516266098.599698Bps" latency="0.000000s"/>
+   <link id="PCI:0000:14:00.0 down" bandwidth="6010515983.677648Bps" latency="0.000000s"/>
+   <link id="PCI:0000:[11-13] up" bandwidth="6517036962.443331Bps" latency="0.000000s"/>
+   <link id="PCI:0000:[11-13] down" bandwidth="6004390320.608641Bps" latency="0.000000s"/>
+   <link id="PCI:0000:[11-13] through" bandwidth="13034073924.886662Bps" latency="0.000000s"/>
+   <link id="PCI:0000:11:00.0 up" bandwidth="6517036962.443331Bps" latency="0.000000s"/>
+   <link id="PCI:0000:11:00.0 down" bandwidth="6004390320.608641Bps" latency="0.000000s"/>
+
+   <route src="CUDA0" dst="CUDA1" symmetrical="NO">
+    <link_ctn id="CUDA0-CUDA1"/>
+    <link_ctn id="PCI:0000:14:00.0 down"/>
+    <link_ctn id="PCI:0000:[14-16] through"/>
+    <link_ctn id="PCI:0000:[14-16] down"/>
+    <link_ctn id="PCI:0000:[10-1f] through"/>
+    <link_ctn id="PCI:0000:[10-1f] down"/>
+    <link_ctn id="Host"/>
+    <link_ctn id="Host"/>
+    <link_ctn id="PCI:0000:[00-0f] up"/>
+    <link_ctn id="PCI:0000:[00-0f] through"/>
+    <link_ctn id="PCI:0000:[06-08] up"/>
+    <link_ctn id="PCI:0000:[06-08] through"/>
+    <link_ctn id="PCI:0000:06:00.0 up"/>
+   </route>
+   <route src="CUDA0" dst="CUDA2" symmetrical="NO">
+    <link_ctn id="CUDA0-CUDA2"/>
+    <link_ctn id="PCI:0000:11:00.0 down"/>
+    <link_ctn id="PCI:0000:[11-13] through"/>
+    <link_ctn id="PCI:0000:[11-13] down"/>
+    <link_ctn id="PCI:0000:[10-1f] through"/>
+    <link_ctn id="PCI:0000:[10-1f] down"/>
+    <link_ctn id="Host"/>
+    <link_ctn id="Host"/>
+    <link_ctn id="PCI:0000:[00-0f] up"/>
+    <link_ctn id="PCI:0000:[00-0f] through"/>
+    <link_ctn id="PCI:0000:[06-08] up"/>
+    <link_ctn id="PCI:0000:[06-08] through"/>
+    <link_ctn id="PCI:0000:06:00.0 up"/>
+   </route>
+   <route src="CUDA0" dst="RAM" symmetrical="NO">
+    <link_ctn id="CUDA0-RAM"/>
+    <link_ctn id="PCI:0000:06:00.0 up"/>
+    <link_ctn id="PCI:0000:[06-08] through"/>
+    <link_ctn id="PCI:0000:[06-08] up"/>
+    <link_ctn id="PCI:0000:[00-0f] through"/>
+    <link_ctn id="PCI:0000:[00-0f] up"/>
+    <link_ctn id="Host"/>
+   </route>
+   <route src="RAM" dst="CUDA0" symmetrical="NO">
+    <link_ctn id="RAM-CUDA0"/>
+    <link_ctn id="PCI:0000:06:00.0 down"/>
+    <link_ctn id="PCI:0000:[06-08] through"/>
+    <link_ctn id="PCI:0000:[06-08] down"/>
+    <link_ctn id="PCI:0000:[00-0f] through"/>
+    <link_ctn id="PCI:0000:[00-0f] down"/>
+    <link_ctn id="Host"/>
+   </route>
+   <route src="CUDA1" dst="CUDA0" symmetrical="NO">
+    <link_ctn id="CUDA1-CUDA0"/>
+    <link_ctn id="PCI:0000:06:00.0 down"/>
+    <link_ctn id="PCI:0000:[06-08] through"/>
+    <link_ctn id="PCI:0000:[06-08] down"/>
+    <link_ctn id="PCI:0000:[00-0f] through"/>
+    <link_ctn id="PCI:0000:[00-0f] down"/>
+    <link_ctn id="Host"/>
+    <link_ctn id="Host"/>
+    <link_ctn id="PCI:0000:[10-1f] up"/>
+    <link_ctn id="PCI:0000:[10-1f] through"/>
+    <link_ctn id="PCI:0000:[14-16] up"/>
+    <link_ctn id="PCI:0000:[14-16] through"/>
+    <link_ctn id="PCI:0000:14:00.0 up"/>
+   </route>
+   <route src="CUDA1" dst="CUDA2" symmetrical="NO">
+    <link_ctn id="CUDA1-CUDA2"/>
+    <link_ctn id="PCI:0000:11:00.0 down"/>
+    <link_ctn id="PCI:0000:[11-13] through"/>
+    <link_ctn id="PCI:0000:[11-13] down"/>
+    <link_ctn id="PCI:0000:[10-1f] through"/>
+    <link_ctn id="PCI:0000:[14-16] up"/>
+    <link_ctn id="PCI:0000:[14-16] through"/>
+    <link_ctn id="PCI:0000:14:00.0 up"/>
+   </route>
+   <route src="CUDA1" dst="RAM" symmetrical="NO">
+    <link_ctn id="CUDA1-RAM"/>
+    <link_ctn id="PCI:0000:14:00.0 up"/>
+    <link_ctn id="PCI:0000:[14-16] through"/>
+    <link_ctn id="PCI:0000:[14-16] up"/>
+    <link_ctn id="PCI:0000:[10-1f] through"/>
+    <link_ctn id="PCI:0000:[10-1f] up"/>
+    <link_ctn id="Host"/>
+   </route>
+   <route src="RAM" dst="CUDA1" symmetrical="NO">
+    <link_ctn id="RAM-CUDA1"/>
+    <link_ctn id="PCI:0000:14:00.0 down"/>
+    <link_ctn id="PCI:0000:[14-16] through"/>
+    <link_ctn id="PCI:0000:[14-16] down"/>
+    <link_ctn id="PCI:0000:[10-1f] through"/>
+    <link_ctn id="PCI:0000:[10-1f] down"/>
+    <link_ctn id="Host"/>
+   </route>
+   <route src="CUDA2" dst="CUDA0" symmetrical="NO">
+    <link_ctn id="CUDA2-CUDA0"/>
+    <link_ctn id="PCI:0000:06:00.0 down"/>
+    <link_ctn id="PCI:0000:[06-08] through"/>
+    <link_ctn id="PCI:0000:[06-08] down"/>
+    <link_ctn id="PCI:0000:[00-0f] through"/>
+    <link_ctn id="PCI:0000:[00-0f] down"/>
+    <link_ctn id="Host"/>
+    <link_ctn id="Host"/>
+    <link_ctn id="PCI:0000:[10-1f] up"/>
+    <link_ctn id="PCI:0000:[10-1f] through"/>
+    <link_ctn id="PCI:0000:[11-13] up"/>
+    <link_ctn id="PCI:0000:[11-13] through"/>
+    <link_ctn id="PCI:0000:11:00.0 up"/>
+   </route>
+   <route src="CUDA2" dst="CUDA1" symmetrical="NO">
+    <link_ctn id="CUDA2-CUDA1"/>
+    <link_ctn id="PCI:0000:14:00.0 down"/>
+    <link_ctn id="PCI:0000:[14-16] through"/>
+    <link_ctn id="PCI:0000:[14-16] down"/>
+    <link_ctn id="PCI:0000:[10-1f] through"/>
+    <link_ctn id="PCI:0000:[11-13] up"/>
+    <link_ctn id="PCI:0000:[11-13] through"/>
+    <link_ctn id="PCI:0000:11:00.0 up"/>
+   </route>
+   <route src="CUDA2" dst="RAM" symmetrical="NO">
+    <link_ctn id="CUDA2-RAM"/>
+    <link_ctn id="PCI:0000:11:00.0 up"/>
+    <link_ctn id="PCI:0000:[11-13] through"/>
+    <link_ctn id="PCI:0000:[11-13] up"/>
+    <link_ctn id="PCI:0000:[10-1f] through"/>
+    <link_ctn id="PCI:0000:[10-1f] up"/>
+    <link_ctn id="Host"/>
+   </route>
+   <route src="RAM" dst="CUDA2" symmetrical="NO">
+    <link_ctn id="RAM-CUDA2"/>
+    <link_ctn id="PCI:0000:11:00.0 down"/>
+    <link_ctn id="PCI:0000:[11-13] through"/>
+    <link_ctn id="PCI:0000:[11-13] down"/>
+    <link_ctn id="PCI:0000:[10-1f] through"/>
+    <link_ctn id="PCI:0000:[10-1f] down"/>
+    <link_ctn id="Host"/>
+   </route>
+
+   <route src="RAM" dst="OpenCL0" symmetrical="NO"><link_ctn id="RAM-OpenCL0"/><link_ctn id="Host"/></route>
+   <route src="OpenCL0" dst="RAM" symmetrical="NO"><link_ctn id="OpenCL0-RAM"/><link_ctn id="Host"/></route>
+   <route src="RAM" dst="OpenCL1" symmetrical="NO"><link_ctn id="RAM-OpenCL1"/><link_ctn id="Host"/></route>
+   <route src="OpenCL1" dst="RAM" symmetrical="NO"><link_ctn id="OpenCL1-RAM"/><link_ctn id="Host"/></route>
+   <route src="RAM" dst="OpenCL2" symmetrical="NO"><link_ctn id="RAM-OpenCL2"/><link_ctn id="Host"/></route>
+   <route src="OpenCL2" dst="RAM" symmetrical="NO"><link_ctn id="OpenCL2-RAM"/><link_ctn id="Host"/></route>
+ </AS>
+ </platform>

+ 130 - 0
tools/perfmodels/sampling/bus/sirocco.platform.v4.xml

@@ -0,0 +1,130 @@
+<?xml version='1.0'?>
+<!DOCTYPE platform SYSTEM "http://simgrid.gforge.inria.fr/simgrid/simgrid.dtd">
+<platform version="4">
+ 
+ 
+ <config id="General">
+   <prop id="network/TCP-gamma" value="-1"></prop>
+   <prop id="network/latency-factor" value="1"></prop>
+   <prop id="network/bandwidth-factor" value="1"></prop>
+ </config>
+ <AS  id="AS0"  routing="Full">
+   <host id="MAIN" speed="1f"/>
+   <host id="CPU0" speed="2000000000f"/>
+   <host id="CPU1" speed="2000000000f"/>
+   <host id="CPU2" speed="2000000000f"/>
+   <host id="CPU3" speed="2000000000f"/>
+   <host id="CPU4" speed="2000000000f"/>
+   <host id="CPU5" speed="2000000000f"/>
+   <host id="CPU6" speed="2000000000f"/>
+   <host id="CPU7" speed="2000000000f"/>
+   <host id="CPU8" speed="2000000000f"/>
+   <host id="CPU9" speed="2000000000f"/>
+   <host id="CPU10" speed="2000000000f"/>
+   <host id="CPU11" speed="2000000000f"/>
+   <host id="CPU12" speed="2000000000f"/>
+   <host id="CPU13" speed="2000000000f"/>
+   <host id="CPU14" speed="2000000000f"/>
+   <host id="CPU15" speed="2000000000f"/>
+   <host id="CPU16" speed="2000000000f"/>
+   <host id="CPU17" speed="2000000000f"/>
+   <host id="CPU18" speed="2000000000f"/>
+   <host id="CPU19" speed="2000000000f"/>
+   <host id="CPU20" speed="2000000000f"/>
+   <host id="CPU21" speed="2000000000f"/>
+   <host id="CPU22" speed="2000000000f"/>
+   <host id="CPU23" speed="2000000000f"/>
+   <host id="CUDA0" speed="2000000000f">
+     <prop id="memsize" value="12079136768"/>
+     <prop id="memcpy_peer" value="1"/>
+   </host>
+   <host id="CUDA1" speed="2000000000f">
+     <prop id="memsize" value="12079136768"/>
+     <prop id="memcpy_peer" value="1"/>
+   </host>
+   <host id="CUDA2" speed="2000000000f">
+     <prop id="memsize" value="12079136768"/>
+     <prop id="memcpy_peer" value="1"/>
+   </host>
+   <host id="CUDA3" speed="2000000000f">
+     <prop id="memsize" value="12079136768"/>
+     <prop id="memcpy_peer" value="1"/>
+   </host>
+   <host id="OpenCL0" speed="2000000000f">
+     <prop id="memsize" value="12079136768"/>
+   </host>
+   <host id="OpenCL1" speed="2000000000f">
+     <prop id="memsize" value="12079136768"/>
+   </host>
+   <host id="OpenCL2" speed="2000000000f">
+     <prop id="memsize" value="12079136768"/>
+   </host>
+   <host id="OpenCL3" speed="2000000000f">
+     <prop id="memsize" value="12079136768"/>
+   </host>
+
+   <host id="RAM" speed="1f"/>
+
+   <link id="Host" bandwidth="10521832623.517040Bps" latency="0.000000s"/>
+
+   <link id="RAM-OpenCL0" bandwidth="7997534022.141151Bps" latency="0.000010s"/>
+   <link id="OpenCL0-RAM" bandwidth="7434276438.572320Bps" latency="0.000012s"/>
+   <link id="RAM-OpenCL1" bandwidth="7978223026.445667Bps" latency="0.000011s"/>
+   <link id="OpenCL1-RAM" bandwidth="7232140009.638909Bps" latency="0.000014s"/>
+   <link id="RAM-OpenCL2" bandwidth="8025122400.678086Bps" latency="0.000011s"/>
+   <link id="OpenCL2-RAM" bandwidth="7300126055.185305Bps" latency="0.000012s"/>
+   <link id="RAM-OpenCL3" bandwidth="8002101228.048121Bps" latency="0.000010s"/>
+   <link id="OpenCL3-RAM" bandwidth="7333165510.983491Bps" latency="0.000012s"/>
+
+   <link id="RAM-CUDA0" bandwidth="10517678844.278971Bps" latency="0.000010s"/>
+   <link id="CUDA0-RAM" bandwidth="10521701010.666672Bps" latency="0.000011s"/>
+   <link id="RAM-CUDA1" bandwidth="10517427805.652538Bps" latency="0.000010s"/>
+   <link id="CUDA1-RAM" bandwidth="10521233123.485935Bps" latency="0.000010s"/>
+   <link id="RAM-CUDA2" bandwidth="10517320202.942270Bps" latency="0.000010s"/>
+   <link id="CUDA2-RAM" bandwidth="10521832623.517040Bps" latency="0.000011s"/>
+   <link id="RAM-CUDA3" bandwidth="10517178916.561483Bps" latency="0.000010s"/>
+   <link id="CUDA3-RAM" bandwidth="10521716373.062309Bps" latency="0.000011s"/>
+
+   <link id="CUDA0-CUDA1" bandwidth="10244090134.034805Bps" latency="0.000012s"/>
+   <link id="CUDA0-CUDA2" bandwidth="7662719221.740685Bps" latency="0.000024s"/>
+   <link id="CUDA0-CUDA3" bandwidth="8527735591.087247Bps" latency="0.000023s"/>
+   <link id="CUDA1-CUDA0" bandwidth="10240684078.899693Bps" latency="0.000012s"/>
+   <link id="CUDA1-CUDA2" bandwidth="7630369996.384952Bps" latency="0.000023s"/>
+   <link id="CUDA1-CUDA3" bandwidth="8542253951.429195Bps" latency="0.000023s"/>
+   <link id="CUDA2-CUDA0" bandwidth="8504224628.018895Bps" latency="0.000024s"/>
+   <link id="CUDA2-CUDA1" bandwidth="8517475744.443908Bps" latency="0.000024s"/>
+   <link id="CUDA2-CUDA3" bandwidth="10232000931.164429Bps" latency="0.000011s"/>
+   <link id="CUDA3-CUDA0" bandwidth="8496220968.849647Bps" latency="0.000023s"/>
+   <link id="CUDA3-CUDA1" bandwidth="8514239613.171523Bps" latency="0.000023s"/>
+   <link id="CUDA3-CUDA2" bandwidth="10242870726.441437Bps" latency="0.000011s"/>
+   <route src="RAM" dst="CUDA0" symmetrical="NO"><link_ctn id="RAM-CUDA0"/><link_ctn id="Host"/></route>
+   <route src="CUDA0" dst="RAM" symmetrical="NO"><link_ctn id="CUDA0-RAM"/><link_ctn id="Host"/></route>
+   <route src="RAM" dst="CUDA1" symmetrical="NO"><link_ctn id="RAM-CUDA1"/><link_ctn id="Host"/></route>
+   <route src="CUDA1" dst="RAM" symmetrical="NO"><link_ctn id="CUDA1-RAM"/><link_ctn id="Host"/></route>
+   <route src="RAM" dst="CUDA2" symmetrical="NO"><link_ctn id="RAM-CUDA2"/><link_ctn id="Host"/></route>
+   <route src="CUDA2" dst="RAM" symmetrical="NO"><link_ctn id="CUDA2-RAM"/><link_ctn id="Host"/></route>
+   <route src="RAM" dst="CUDA3" symmetrical="NO"><link_ctn id="RAM-CUDA3"/><link_ctn id="Host"/></route>
+   <route src="CUDA3" dst="RAM" symmetrical="NO"><link_ctn id="CUDA3-RAM"/><link_ctn id="Host"/></route>
+   <route src="CUDA0" dst="CUDA1" symmetrical="NO"><link_ctn id="CUDA0-CUDA1"/><link_ctn id="Host"/></route>
+   <route src="CUDA0" dst="CUDA2" symmetrical="NO"><link_ctn id="CUDA0-CUDA2"/><link_ctn id="Host"/></route>
+   <route src="CUDA0" dst="CUDA3" symmetrical="NO"><link_ctn id="CUDA0-CUDA3"/><link_ctn id="Host"/></route>
+   <route src="CUDA1" dst="CUDA0" symmetrical="NO"><link_ctn id="CUDA1-CUDA0"/><link_ctn id="Host"/></route>
+   <route src="CUDA1" dst="CUDA2" symmetrical="NO"><link_ctn id="CUDA1-CUDA2"/><link_ctn id="Host"/></route>
+   <route src="CUDA1" dst="CUDA3" symmetrical="NO"><link_ctn id="CUDA1-CUDA3"/><link_ctn id="Host"/></route>
+   <route src="CUDA2" dst="CUDA0" symmetrical="NO"><link_ctn id="CUDA2-CUDA0"/><link_ctn id="Host"/></route>
+   <route src="CUDA2" dst="CUDA1" symmetrical="NO"><link_ctn id="CUDA2-CUDA1"/><link_ctn id="Host"/></route>
+   <route src="CUDA2" dst="CUDA3" symmetrical="NO"><link_ctn id="CUDA2-CUDA3"/><link_ctn id="Host"/></route>
+   <route src="CUDA3" dst="CUDA0" symmetrical="NO"><link_ctn id="CUDA3-CUDA0"/><link_ctn id="Host"/></route>
+   <route src="CUDA3" dst="CUDA1" symmetrical="NO"><link_ctn id="CUDA3-CUDA1"/><link_ctn id="Host"/></route>
+   <route src="CUDA3" dst="CUDA2" symmetrical="NO"><link_ctn id="CUDA3-CUDA2"/><link_ctn id="Host"/></route>
+
+   <route src="RAM" dst="OpenCL0" symmetrical="NO"><link_ctn id="RAM-OpenCL0"/><link_ctn id="Host"/></route>
+   <route src="OpenCL0" dst="RAM" symmetrical="NO"><link_ctn id="OpenCL0-RAM"/><link_ctn id="Host"/></route>
+   <route src="RAM" dst="OpenCL1" symmetrical="NO"><link_ctn id="RAM-OpenCL1"/><link_ctn id="Host"/></route>
+   <route src="OpenCL1" dst="RAM" symmetrical="NO"><link_ctn id="OpenCL1-RAM"/><link_ctn id="Host"/></route>
+   <route src="RAM" dst="OpenCL2" symmetrical="NO"><link_ctn id="RAM-OpenCL2"/><link_ctn id="Host"/></route>
+   <route src="OpenCL2" dst="RAM" symmetrical="NO"><link_ctn id="OpenCL2-RAM"/><link_ctn id="Host"/></route>
+   <route src="RAM" dst="OpenCL3" symmetrical="NO"><link_ctn id="RAM-OpenCL3"/><link_ctn id="Host"/></route>
+   <route src="OpenCL3" dst="RAM" symmetrical="NO"><link_ctn id="OpenCL3-RAM"/><link_ctn id="Host"/></route>
+ </AS>
+ </platform>