Clock: STREAM (frequency 100.0 MHz phase 0.0 duty cycle 0.5 static)
	[STREAM] addrgen_cmd_MemoryControllerPro0_oDataT2 (ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_oDataT2)
	[STREAM] addrgen_cmd_MemoryControllerPro0_oDataT1 (ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_oDataT1)
	[STREAM] addrgen_cmd_MemoryControllerPro0_inBT2 (ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_inBT2)
	[STREAM] addrgen_cmd_MemoryControllerPro0_inAT3 (ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_inAT3)
	[STREAM] addrgen_cmd_MemoryControllerPro0_inBT3 (ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_inBT3)
	[STREAM] addrgen_cmd_MemoryControllerPro0_inAT2 (ManagerStateMachine_addrgen_cmd_MemoryControllerPro0_inAT2)
	[STREAM] Stream_58 (Fifo)
	[STREAM] Stream_50 (Fifo)
	[STREAM] Stream_42 (Fifo)
	[STREAM] Stream_62 (Fifo)
	[STREAM] Stream_54 (Fifo)
	[STREAM] Stream_46 (Fifo)
	[STREAM] Stream_104 (Fifo)
	[STREAM] Stream_100 (Fifo)
	[STREAM] Stream_96 (StreamPullPushAdapter)
	[STREAM] Stream_90 (Fifo)
	[STREAM] Stream_90 (Fifo)
	[STREAM] Stream_60 (DualAspectReg)
	[STREAM] Stream_92 (StreamPullPushAdapter)
	[STREAM] Stream_8 (DualAspectMux)
	[STREAM] Stream_108 (Fifo)
	[STREAM] Stream_108 (Fifo)
	[STREAM] Stream_112 (Fifo)
	[STREAM] Stream_112 (Fifo)
	[STREAM] Stream_10 (DualAspectMux)
	[STREAM] MemoryControllerPro0 (ManagerStateMachine_MemoryControllerPro0)
	[STREAM] MemoryControllerPro0 (ManagerStateMachine_MemoryControllerPro0)
	[STREAM] Stream_12 (DualAspectMux)
	[STREAM] Stream_14 (DualAspectMux)
	[STREAM] Stream_116 (Fifo)
	[STREAM] Stream_116 (Fifo)
	[STREAM] Stream_120 (Fifo)
	[STREAM] Stream_120 (Fifo)
	[STREAM] StreamFMAKernel (Kernel)
	[STREAM] Stream_122 (Fifo)
	[STREAM] Stream_94 (Fifo)
	[STREAM] Stream_94 (Fifo)
	[STREAM] Stream_64 (DualAspectReg)
Clock: DDR_CLK_a (frequency 266.6 MHz phase 0.0 duty cycle 0.5 static)
	[DDR_CLK_a] Stream_84 (Fifo)
	[DDR_CLK_a] MemoryControllerInterface_a (MemoryControllerInterface_a)
	[DDR_CLK_a] Stream_34_pipeline_4 (Stream_34_pipeline)
	[DDR_CLK_a] Stream_68 (Fifo)
Clock: DDR_CLK_b (frequency 266.6 MHz phase 0.0 duty cycle 0.5 static)
	[DDR_CLK_b] Stream_80 (Fifo)
	[DDR_CLK_b] MemoryControllerInterface_b (MemoryControllerInterface_b)
	[DDR_CLK_b] Stream_29_pipeline_4 (Stream_29_pipeline)
	[DDR_CLK_b] Stream_72 (Fifo)
Clock: PCIE (frequency 125.0 MHz phase 0.0 duty cycle 0.5 static)
	[PCIE] inAT1 (PCIe_From_Host)
	[PCIE] inBT1 (PCIe_From_Host)
	[PCIE] Stream_98 (Fifo)
	[PCIE] Stream_98 (Fifo)
	[PCIE] Stream_102 (Fifo)
	[PCIE] Stream_102 (Fifo)
	[PCIE] Stream_4 (DualAspectMux)
	[PCIE] Stream_1 (DualAspectMux)
	[PCIE] Stream_104 (Fifo)
	[PCIE] Stream_100 (Fifo)
	[PCIE] Stream_124 (StreamPullPushAdapter)
	[PCIE] oDataT3 (PCIe_To_Host)
	[PCIE] Stream_122 (Fifo)
	[PCIE] Stream_20 (DualAspectReg)
Clock: MemoryControllerPro0_clk (frequency 272.5 MHz phase 0.0 duty cycle 0.5 static)
	[MemoryControllerPro0_clk] Stream_58 (Fifo)
	[MemoryControllerPro0_clk] Stream_50 (Fifo)
	[MemoryControllerPro0_clk] Stream_42 (Fifo)
	[MemoryControllerPro0_clk] Stream_62 (Fifo)
	[MemoryControllerPro0_clk] Stream_54 (Fifo)
	[MemoryControllerPro0_clk] Stream_46 (Fifo)
	[MemoryControllerPro0_clk] Stream_28_pipeline_4 (Stream_28_pipeline)
	[MemoryControllerPro0_clk] Stream_80 (Fifo)
	[MemoryControllerPro0_clk] Stream_72 (Fifo)
	[MemoryControllerPro0_clk] Stream_84 (Fifo)
	[MemoryControllerPro0_clk] Stream_68 (Fifo)
	[MemoryControllerPro0_clk] Stream_76 (Fifo)
	[MemoryControllerPro0_clk] MemoryControllerPro0 (ManagerStateMachine_MemoryControllerPro0)
	[MemoryControllerPro0_clk] MemoryControllerPro0_IntSource (MemoryInterruptSource)
	[MemoryControllerPro0_clk] Stream_38_pipeline_4 (Stream_38_pipeline)
	[MemoryControllerPro0_clk] Stream_33_pipeline_4 (Stream_33_pipeline)
	[MemoryControllerPro0_clk] Stream_88 (Fifo)
Clock: DDR_CLK_c (frequency 266.6 MHz phase 0.0 duty cycle 0.5 static)
	[DDR_CLK_c] Stream_39_pipeline_4 (Stream_39_pipeline)
	[DDR_CLK_c] Stream_76 (Fifo)
	[DDR_CLK_c] Stream_88 (Fifo)
	[DDR_CLK_c] MemoryControllerInterface_c (MemoryControllerInterface_c)
